Channel-width dependent hot-carrier degradation of thin-gate pMOSFETs

Lee, Y.-H.; Wu, K.; Linton, T.; Mielke, N.; Hu, Shiliang; Wallace, B.D.

doi:10.1109/relphy.2000.843894

Cited by 8 publications

(2 citation statements)

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“…Even though hot-carrier phenomena have widely been studied in MOS poly-TFT structures [39], their quantitative [40] impact in the reliability and performance characteristics of poly-TFT devices of different channel widths after electrical stressing under different stressing conditions has been described only to a limited extent. Moreover, even in the models developed for the mature technology of silicon-on-insulator devices [41], typical bulk MOSFETs [42], and a-Si:H TFTs [43], the effect of subjecting devices with various channel widths under different hot-carrier stress conditions has not been analyzed, and mainly shallow trench isolation p-type MOS devices were examined [44]. Consequently, the effect of different hot-carrier stressing conditions on the 1-D currentvoltage characteristics as a function of the channel width needed to be further examined.…”

Section: Degradation Modelingmentioning

confidence: 99%

Technology, performance and degradation characteristics of SLS ELA thin film transistors

et al. 2013

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Low temperature polycrystalline silicon thin film transistors (LTPS poly-Si TFTs) are essential for large area electronics and high performance flat panel displays. In recent years, LTPS TFT performance has substantially increased due to the important breakthroughs in the field of polycrystalline silicon crystallization and also due to the optimization of the process steps that differ from those of typical MOSFETs, mainly because of the requirement for low temperature procedures. In this review we present the electrical characteristics of polycrystalline silicon TFTs, crystallized with different variations of the advanced SLS ELA technique, and the determination of process technological parameters that affect the device performance, in order to further optimize the production of such high performance transistors, in terms of poly-Si microstructure, channel dimensions and topology. Also, the effect of these fabrication parameters on device degradation characteristics is studied, with an attempt to model and predict degradation characteristics.

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Section: Degradation Modelingmentioning

confidence: 99%

Technology, performance and degradation characteristics of SLS ELA thin film transistors

et al. 2013

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“…The device degradation is closely related to its horizontal structure, which makes people believe that the horizontal structure must be taken as one of the important factors. [14][15][16][17][18] Therefore, in this paper, we focus on the effect of PMOSFET gate length on the relationship of parameter degradation under the NBTI stress, including threshold voltage, mobility, and drain current. It is obvious that they have a close correlation.…”

Section: Introductionmentioning

confidence: 99%