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This paper described the shadow moiré measurement of bare flip chip coreless and standard (3/2/3) BGA substrate to inspect the change of each thermal history (0hr, after pre-baking, IR-reflow), the warpage increased significantly on IR reflow peak temperature and largest warpage located around the C4 area of coreless FCBGA substrate and standard FCBGA substrate change was not obvious. Electrical performance was simulated by Ansoft Q3D and HFSS software, the coreless flip chip BGA substrate showed higher insertion loss and lower return loss than standard (3/2/3) flip chip BGA substrate. Bump stress, die stress and Cu trace stress of substrate were simulated by FEA (Finite Element Analysis) method, the results indicate that coreless flip chip BGA performs lower die stress and bump stress and higher trace stress than standard (3/2/3) flip-chip BGA. Furthermore, this study also found out the optimal assembly process condition. For the reliability evaluation, all of packages were subjected to pre-condition of JEDEC Level 3, TCT (Temperature Cycling Test), HTSL (High temperature Storage Life) and HAST (High accelerated stress test) and the results showed passed.

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In this paper, we studied the wire bonding ability and the solder joint reliability for Electrolytic Ni/Au and ENEPIG. For studying wire bonding ability, 4N wire with 20um in diameter was used. Pull strength of Au wire and failure mode after each pull test were both the criteria of wire bonding. After wire pull test, the pull strength and failure mode of Electrolytic Ni/Au and ENEPIG were similar. Therefore, it could be supposed the wire bonding ability of ENEPIG is similar with Electrolytic Ni/Au. For solder joint reliability, different types of solder joint test were conductedconventional ball shear test, cold-ball pull test. High speed ball shear test was also applied to simulate high strain rate loading, similar as drop test. Failure mode and micro analysis were carried out by the analytical tools, including Scanning Electron Microscope (SEM) and Energy Dispersive Spectrometer (EDX).In addition, samples were performed thermal process, like multi reflow (as-soldering, 3x, 6x) and solid aging (duration: 250, 500, 1000 hours at 150 0 C). Interfacial reaction of two type surface finish with solder ball, Sn96.5Ag3Cu0.5 (SAC305), were observed by SEM for different thermal process. Cross section image and morphology image were observed to study IMC appearance. And EDX was also used to confirm the IMC phase From the ball shear test results, it was no obvious difference after multi reflow times and different solid aging duration for Electrolytic Ni/Au and ENEPIG. The failure mode of Electrolytic Ni/Au and ENEPIG were both broken at solder. Cold-ball pull test showed Electrolytic Ni/Au and ENEPIG have similarly failure mode distribution after multi reflow process and solid aging process. In the high speed ball shear test, the behavior of broken interface was quite different between Electrolytic Ni/Au and ENEPIG. For as-soldering samples, the broken interface of Electrolytic Ni/Au usually happened at intermetallic compound (IMC) phase, but the ENEPIG usually happened at solder phase. Besides, samples are tested with different test speed to observed the transition point of failure mode that from ductile to brittle. The results showed the transition point of Electrolytic Ni/Au was prior to ENEPIG. On the other hand, the high speed shear test results of ENEPIG after performing solid aging showed lower IMCbroken percentage than Electrolytic Ni/Au. It could be deduced that ENEPIG has better solder joint quality.

Stack-die package concept has been emerging 2-3 years ago. The major product -stack-die package with Flash and SRAM chips integrated together which is driven by cellular phone for the purpose of size and weight reduction. The basic requirement for these two dies in stacked package is the size difference must be large enough to allow wire bonding process at bottom die if we still want to utilize the low cost, mature wire bonding technology in interconnection. However, this requirement will limit the application in trying to integrate two similar or same size dies into one stack-die package.