We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS) / high-k dielectric and metal-in-collar (MIC), and lowk inter-level dielectric (ILD) are demonstrated. IntroductionAs shown in a previous paper, the trench DRAM technology can be extended down to 70nm by using a [100] rotated substrate and a checkerboard trench layout (1). For the further scaling of this trench cell architecture to sub 60nm feature sizes major technology and device challenges have to be addressed:

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This work presents the structure Junctionless FinFET (JLFinFET) based on ultra-thin body (UTB) with double stacked Si3N4 charge trapping layer (NN-CTL) Si-SiO2-Si3N4-Si3N4-SiO2-Si (SONNOS) nonvolatile memory (NVM). The device shows excellent transistor performances including steep sub-threshold swing (SS) of 76 mV/dec, favorable Vth, and high Ion/Ioff ratio (>107). For n-channel device, it shows excellent memory characteristics, high program/erase (P/E) performance, good endurance (>104 cycles) and an excellent 95∼99% electron retention at 85°C for 10 years.