This paper presents a 1/2.3-inch 10.3Mpixel Back-Illuminated (BI) CMOS image sensor that targets both digital still camera (DSC) and high-definition camcorder applications. These applications require high-pixel-count, high-sensitivity, high saturation signal, low noise and high-speed imaging for image quality [1]. The sensor is scaled down to get a higher resolution due to higher pixel count. Several approaches such as a Cu process to reduce the pixel height and inner micro-lenses to gather rays of incident light have been proposed to overcome electro-optical challenges [2][3][4]. The BI process has been reported as one of the most promising technologies to improve optical performance [5,9]. This BI image sensor includes a 10b/12b analog-to-digital converter (ADC), an internal phase-locked loop (PLL) and a 10b serial LVDS interface to enable a data-rate up to 576MHz.Pixel sharing increases the sense-node capacitances because of: floating-diffusion (FD) regions linked in series, and interconnect capacitance. The FD capacitance causes a trade-off between conversion gain and full well capacity [4,6]. The imager uses a 1.65×1.65µm 2 4-shared-pixel FD boost-driving architecture with a view to optimize for high fill factor, high conversion gain and high full well capacity.

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We have developed a 1/2.3-in. 10.3 mega pixel back-illuminated CMOS image sensor utilizing serial multiple sampling. This sensor achieves an RMS random noise of 1.3e− and row temporal noise (RTN) of 0.19e−. Serial multiple sampling is realized with a column inline averaging technique without the need for additional processing circuitry. Pixel readout is accomplished utilizing a 4-shared-pixel floating diffusion (FD) boost-driving architecture. RTN caused by column parallel readout was analyzed considering the transfer function at the system level and the developed model was verified by measurement data taken at each sampling time. This model demonstrates the RTN improvement of −1.6 dB in a parallel multiple readout architecture.