, and Li Zhao-Ji( ) a)

This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor (LDMOS) with selfadaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (E I ) and increase breakdown voltage (BV). The BV and E I of SAC LDMOS increase to 612 V and 600 V/µm from 204 V and 90.7 V/µm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on E I are defined and analysed.

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141 V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (VB,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n + -regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n + -regions on the interface by the force with ionized donors in the undepleted n + -regions, and therefore effectively enhance the electric field of the dielectric buried layer (E I ) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E I of the CI PSOI LDMOS increase to 631 V and 584 V/µm from 246 V and 85.8 V/µm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.