A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

Abstract

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n + -regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n + -regions on the interface by the force with ionized donors in the undepleted n + -regions, and therefore effectively enhance the electric field of the dielectric buried layer (E I ) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E I of the CI PSOI LDMOS increase to 631 V and 584 V/µm from 246 V and 85.8 V/µm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.

Characteristics and Breakdown Behaviors of Polysilicon Resistors for High Voltage Applications

“…The above results suggest that, in order to ensure that the resistor behaves robustly in the circuits, the study on the breakdown voltage of the resistor with different sizes is required. Besides, the voltage stress should be a necessary item for the reliability evaluation including both self-heating and electromigration effects of polysilicon resistors [12][13][14][15][16].…”