The European project DOTFIVE [1] addresses evolutionary scaling of self-aligned selective epitaxial base SiGe:C HBTs, investigates novel SiGe:C HBT architectures, and develops novel process modules to push SiGe BiCMOS towards 500 GHz F max and 2.5 ps gate delay. In this paper, scaling issues of SiGe:C HBT technology will be addressed. The limitations of the different commonly used architectures will be described, and measures taken in the project to overcome these limitations will be summarized. Initial results indicate that the objectives of the project can be reached.