0.18 μm SiGe BiCMOS technology for wireless and 40 Gb/s communication products

Schuegraf, K.; Racanelli, M.; Kalburge, A.; Shen, Bo; Hu, Chun; Chapek, D.; Howard, David; Quon, D.; Feiler, D.; Dornisch, D.; U’Ren, G. D.; Abdulridha, Hawraa A.; Zheng, Jian; Zhang, Jinshu; Bell, K.; Ring, K.; Yin, K.; Joshi, P.; Akhtar, S.; Lee, T.; Kempf, P.

doi:10.1109/bipol.2001.957878

Cited by 17 publications

(5 citation statements)

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“…Currently, chip manufacturers focus mainly on the integration of Si 1Ϫx Ge x in heterojunction bipolar transistors ͑HBT͒ in Bi complementary metal oxide semiconductor ͑BiCMOS͒ technology. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] In a next phase, attention goes to the fabrication of Si/Si 1Ϫx Ge x heterojunction CMOS devices to improve the performance of the p-type metal oxide semiconductor ͑MOS͒ device, [16][17][18][19][20][21][22][23][24] and to elevated Si 1Ϫx Ge x source/drain contacts to reduce short channel effects in CMOS technology. [25][26][27][28][29] For the first two applications, both selective and nonselective epitaxial growth by means of chemical vapor deposition ͑CVD͒ can be used.…”

mentioning

confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

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Si 1Ϫx Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1Ϫx Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity ͑microloading on a micrometer scale and gas depletion on a wafer scale͒ and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1Ϫx Ge x growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content ͑no microloading͒ and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (ϳ2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of Si 1Ϫx Ge x heterojunction bipolar transistors ͑0.35 and 0.25 m technology͒, and p-type Si 1Ϫx Ge x heterojunction metal oxide semiconductor devices ͑effective gate length down to 70 nm͒.

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confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

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“…The HS and HV HBTs share the same emitter and base structure and the same footprint. The difference lies in collector where the HS HBT has a heavily doped pedestal collector very close to base [5]. The measurement shows that the R TH of the HS transistors changes little over the same bias range.…”

Section: Measurement Resultsmentioning

confidence: 93%

“…The SiGe HBT used in the R TH investigation is fabricated in Jazz Semiconductor's 0.18 µm BiCMOS technology with deep trench isolation [5]. To achieve high breakdown voltage for wireless PA applications, this technology incorporates a thick collector epitaxial layer.…”

Section: Measurement Resultsmentioning

confidence: 99%

Kirk Effect Induced Bias Dependency of Thermal Resistance in SiGe HBTs

Jiang

Jiao²,

Racanelli³

2008

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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“…9 STI and DTI have now evolved to a common isolation in SiGe BiCMOS technologies. [10][11][12][13] However, there have not been many articles addressing the isolation process details in depth.…”

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confidence: 99%

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

Forsberg

Johansson

Liu

et al. 2004

J. Electrochem. Soc.

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A shallow and deep trench isolation process module for high performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ is presented in detail. The shallow trench is etched prior to the deep trench, allowing the deep trench to be placed self-aligned to the shallow trench edge. By planarizing the polycrystalline silicon deep trench filling using chemical mechanical polishing ͑CMP͒ before etchback, the recess into deep trenches is decreased and polysilicon spacer formation at the active area edges is avoided. The poly CMP is stopped before all polysilicon in the active area is removed, to avoid polysilicon dishing and erosion of oxide on top of nitride on active area. Important issues arising during process development are discussed. Two different slurries were evaluated, which resulted in two different nonuniformities of polysilicon thickness. Nonuniformity transfers partially down to a range of recesses into the deep trenches, but the recesses were much smaller compared to the etchback only. Highdensity chemical vapor deposition was used for shallow trench filling and a direct shallow trench isolation-CMP process was developed. The feasibility of the process module was demonstrated using a 0.25 m, 200 mm bipolar double-poly rf process with optional SiGe epi base. Electrical results from completed transistors are presented to verify the function of the module.All nontrivial integrated electronics involve connecting isolated devices through specific electrical connection paths. The device isolation scheme is, therefore, one of the critical parts for integrated circuit processes. Many different schemes have been developed over the years. Parameters like minimum isolation spacing, surface planarity, defect density, process complexity, and electrical properties ͑dc and high frequency͒ influence the choice of a scheme for the particular application and process technology. Mesa isolation, junction isolation, and localized oxidation of silicon ͑LOCOS͒ are techniques in use. As feature sizes continue to decrease, there is a need to reduce shortcomings, such as low packing density, high leakage currents, and latch-up between devices, associated with older isolation technologies.In complementary metal-oxide-semiconductor ͑CMOS͒ technology, LOCOS has been replaced by shallow trench isolation ͑STI͒. 1,2 The lateral encroachment into the active area when using LOCOS, due to oxidation under the nitride at the edges, can be avoided by using STI. Thereby, the lateral control increases, tighter design rules can be applied, and parasitic capacitances are reduced. STI also offers a more planar surface and the possibility to increase the field oxide thickness.A complexity in high-performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ processes is the integration of STI with deep trench isolation ͑DTI͒. Deep trenches, usually with a depth larger than a couple of micrometers, are mainly used to isolate different devices and device groups ͑wells͒ in CMOS/ BiCMOS technology. The trenches are filled with oxide...

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0.18 μm SiGe BiCMOS technology for wireless and 40 Gb/s communication products

Cited by 17 publications

References 0 publications

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Kirk Effect Induced Bias Dependency of Thermal Resistance in SiGe HBTs

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

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