2020 IEEE International Solid- State Circuits Conference - (ISSCC) 2020
DOI: 10.1109/isscc19947.2020.9063027
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12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters

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Cited by 16 publications
(9 citation statements)
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“…While a better power efficiency for a higher datarate is obtained for the coherent transmitter in [22], the transmitter has around 3 dB peaking in its EO response, and quite some equalization will be required to flatten this response and avoid degradation in the PAM4 eye. In the case of [22], this equalization is provided by the digital signal processing required for the coherent experiments. This is undesired for short-reach datacenter interconnects employing PAM4, as additional equalization increases the total link power consumption and the link latency.…”
Section: Resultsmentioning
confidence: 99%
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“…While a better power efficiency for a higher datarate is obtained for the coherent transmitter in [22], the transmitter has around 3 dB peaking in its EO response, and quite some equalization will be required to flatten this response and avoid degradation in the PAM4 eye. In the case of [22], this equalization is provided by the digital signal processing required for the coherent experiments. This is undesired for short-reach datacenter interconnects employing PAM4, as additional equalization increases the total link power consumption and the link latency.…”
Section: Resultsmentioning
confidence: 99%
“…This is undesired for short-reach datacenter interconnects employing PAM4, as additional equalization increases the total link power consumption and the link latency. No transmission experiments without additional DSP are shown in [22], prohibiting a correct comparison. Comparing the presented transmitter to the other references, we can show the best power efficiency at 50 and 53 Gbaud thanks to the use of the limiting driver coupled to a segmented traveling-wave modulator and thorough co-design of the driver and modulator.…”
Section: Resultsmentioning
confidence: 99%
“…Nowadays, the typical high-baud rate optical transmitters rely on digital signal processing (DSP), a digital-to-analog conversion (DAC), a modulator driver, and an optical I/Q modulator [1], [2], [3]. The next-generation (coherent) transmitters use dualpolarization, I/Q modulation, and pulse amplitude modulation (PAM) techniques to boost the overall transmitting data rate to exceed 800 Gb/s [1], [2]. This requires the integrated RF components to feature a wide bandwidth and a low THD.…”
mentioning
confidence: 99%
“…The output swing of modulator drivers in CMOS is usually below 3 Vppd [2], [8], [9] as it is limited by the device breakdown voltage, which is technology-dependent. In recent years, drivers designed in technologies such as SiGe BiCMOS [10], [11], [12], [13], [14], [15], and InP DHBT [16], [17], [18] have been investigated because they have a collectorto-emitter breakdown voltage BV CEO over 1.5 V and f T / f MAX above 300 GHz.…”
mentioning
confidence: 99%
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