12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

Lee, Yeonho; Choi, Yoonjae; Song, Junyoung; Hwang, Sun Jin; Bae, Sang-Geun; Jun, Jaehun

doi:10.1109/jssc.2018.2878814

Cited by 7 publications

(2 citation statements)

References 7 publications

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“…M EETING the ever-increasing demand for higher resolution, color depth, and refresh rate TVs requires high-throughput display driver integrated circuits (DDIs). A DDI receives high-speed data from the timing controller (TCON) and drives it to the pixel drivers [1]- [3]. In a typical 4K (UHD) TV, the throughput for each DDI is 3 Gb/s and is expected to increase to 5.2 Gb/s for the next-generation 8K (Quad-UHD) TVs.…”

Section: Introductionmentioning

confidence: 99%

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

Wang

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a high-speed receiver for nextgeneration 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be co-integrated with pixel drivers in the DDI, it must be implemented in a process with high-voltage devices, which poses significant challenges in achieving beyond 5-Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time linear equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180-nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29-dB channel loss while consuming 120 mA from a 1.8-V supply.

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Section: Introductionmentioning

confidence: 99%

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

Wang

et al. 2022

IEEE J. Solid-State Circuits

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“…Introduction: As high-resolution display systems require the massive transmission of graphic data, data rates of high-speed interfaces for display SoCs continue to grow. For example, intra-panel interfaces to support 5-10 Gb/s per-lane data rates for 8K displays and 15+Gb/s for next-generation ones [1][2][3]. However, the channel bandwidths of such display systems are severely limited due to loss and reflections from long PCB traces and FPC (Flexible Printed Circuit) structures.…”

mentioning

confidence: 99%

A 16.7-Gb/s full-transition avoidance PAM-4 2-tap FFE transmitter with shunt switches for display interfaces

Han

Song

Seo

et al. 2022

Preprint

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This paper describes a channel-loss-tolerant 16.7-Gb/s PAM-4 transmitter with feed-forward equalization (FFE) for display interfaces. The proposed transmitter adopts full transition avoidance (FTA) coding in combination with the 2-tap FFE to enhance the worst-case horizontal eye-opening in the presence of inter-symbol interference (ISI) and shunt switches to reduce power consumption. The transmitter test chip was fabricated in a 28-nm CMOS process and occupied 0.04 mm2. The design achieved 16.7-Gb/s (corresponding to 10 Gbaud/s) with a 0.20x wider horizontal eye-opening for a >7.2 dB loss channel while consuming 107.6mW (corresponding to 6.4 pJ/bit) from the 1.2-V supply.

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24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient Braid Clock Signaling With Fixed Embedded Transition for 8K-UHD Intrapanel Interface

Lee

Choi

2019

IEEE Solid-State Circuits Lett.

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12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

Cited by 7 publications

References 7 publications

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

A 16.7-Gb/s full-transition avoidance PAM-4 2-tap FFE transmitter with shunt switches for display interfaces

24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient Braid Clock Signaling With Fixed Embedded Transition for 8K-UHD Intrapanel Interface

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