13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

Kiene, Gerd; Catania, Alessandro; Overwater, Ramon; Bruschi, P.; Charbon, Edoardo; Babaie, Masoud; Foti, Sebastiano

doi:10.1109/isscc42613.2021.9365927

Cited by 25 publications

(27 citation statements)

References 4 publications

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“…All these works show that SH is exacerbated at cryogenic temperatures and that the effect is highly dependent on device geometry (size, aspect ratio) and power density. This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC with low power density [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density.…”

Section: Imentioning

confidence: 90%

“…This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC with low power density [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density. Understanding the impact of SH is especially crucial for the cryo-CMOS low-noise amplifiers (LNA) necessary for the detection of the weak signals from quantum processors, as an increase of the device temperature of only a few Kelvin can strongly affect the noise performance, e.g., in a thermal-noiselimited amplifier in which the noise is directly proportional to the device temperature.…”

Section: Imentioning

confidence: 90%

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Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Hart

Babaie

Vladimirescu

et al. 2021

IEEE J. Electron Devices Soc.

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This work presents a self-heating study of a 40nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 µm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full selfheating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

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Section: Imentioning

confidence: 90%

Section: Imentioning

confidence: 90%

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Hart

Babaie

Vladimirescu

et al. 2021

IEEE J. Electron Devices Soc.

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show abstract

“…All these works show that SH is exacerbated at cryogenic temperatures and that the effect is highly dependent on device geometry (size, aspect ratio) and power density. This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density.…”

Section: Imentioning

confidence: 86%

“…This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density. Understanding the impact of SH is especially crucial for the cryo-CMOS low-noise amplifiers (LNA) necessary for the detection of the weak signals from quantum processors, as an increase of the device temperature of only a few Kelvin can strongly affect the noise performance, e.g., in a thermal-noiselimited amplifier in which the noise is directly proportional to the device temperature.…”

Section: Imentioning

confidence: 86%

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Hart¹,

Babaie²,

Vladimirescu³

et al. 2021

Preprint

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“…This requires significant breakthroughs to drastically increase the operational temperature of qubits ("hot qubits") and reduce power consumption of the control/detect circuitry, while simultaneously improving the qubit performance in terms of uniformity and fidelity. The very recent publications in [43], [44] present a quantum read-out circuitry that works at cryogenic temperature but still exhibits high power consumption per qubit, which makes it difficult to scale for a higher number of qubits. In other very recent publications [45], [46], RF-reflectometry based read-out circuitry is presented that relies on a multiplexing technique to cover the output data of all associated qubits due to the large needed area for the read-out circuitry alone.…”

mentioning

confidence: 99%

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Staszewski

Esmailiyan²,

Wang

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm FD-SOI CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector.The SoC operates at a cryogenic temperature of 3.4 K. The occupied area of each QD array is 0.7×0.4 µm 2 , while each QD occupies only 20×80 nm 2 . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. Position of the injected charge inside the QD array is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QD array consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.Index Terms-Capacitive DAC (CDAC), charge qubits, cryo-CMOS, fully depleted silicon-on-insulator (FD-SOI), imposer, positionbased qubits, quantum computer (QC), quantum dot (QD), single-electron detector, single-electron injector. I. INTRODUCTIONQ UANTUM computing is a new paradigm that utilizes the fundamental principles of quantum mechanics, such as superposition, interference and entanglement [1], [2]. The range of complex problems from mathematics, chemistry and material science that could be solved with quantum computing is far beyond the reach of today's most powerful supercomputers. The potential is thus immense. Quantum bits (qubits), basic units of quantum information, operate at a molecular/atomic level. They are extremely fragile and difficult to manipulate and read out. Some quantum computer technologies, such as based on trapped ions and photons, do not require the equipment to be cryogenically cooled [3], [4], but the majority of qubits must operate under extremely low Manuscript received

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13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

Cited by 25 publications

References 4 publications

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

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