18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Abstract

Demand for higher bandwidth DRAM continues to increase, especially in highperformance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced [1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2 nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.HBM is composed of stacked DRAM dies over a buffer die as shown in Fig. 18.2.1. All 3 configurations of HBM are shown on the right upper side. The thickness of the top core die is different depending on the number of stacks used, but the total height of the HBM is the same regardless of the number of stacks for compatibility. The purpose of the buffer die is to 1) provide routes from the TSVs related to the DRAM dies to the micro bump IOs in the PHY area. 2) provide test functionality to system makers and DRAM vendors; DRAM tests are all executed through DA (direct access) PADs. Figure 18.2.1 shows that the test block covers all of the normal paths from the PHY to the TSV for each test item. Functionality and timing margins can be guaranteed by this architecture since a DFT and a SerDes module with a PLL block is implemented for low frequency test equipment. BIST and IEEE1500 blocks support HBM tests on silicon in package (SiP) since it is difficult and inconvenient to test HBM after the chip on wafer (CoW) process is completed and the HBM is connected to a processor. System makers can test HBMs using these functions and isolate failure points when they occur. Figure 18.2.2 shows the architecture of the core die (DRAM die). Each die has a 9Gb cell array including 1Gb cells for optional ECC. The upper diagram shows two configurations for 4H/8H and 2H cases: where 4H means that four core dies are stacked over the buffer die. In 4H/8H case the HBM is composed of two channels and each channel has two pseudo channels (PC0/PC1) which consists of 16 banks (4 bank-groups ...

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

“…TSVs with micro-bumps are conventionally used for the high-bandwidth memory (HBM) [82][83][84][85][86][87], as shown in Figure 29. However, there are several issues when using micro-bumps.…”

“…GPU/CPU vendors are constantly striving to increase the speed of their products, for example, to 2 TB/s and 4 TB/s, focusing on AI systems. HBM will have to increase the I/O pin speed by 2.5 times, such as the 5.0 Gb/s/pin [87] from the 2.0 Gb/s/pin [84], and therefore, power and heat will also be increased.…”

“…Figure29. HBM road map with micro-bumps, where HBM[82], HBM2[83][84][85], HBM2E[86,87], respectively.…”

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes

“…For vault controllers and the SMC controller previously developed models in [25] and [24] were used (all in 28nm FDSOI), the serial link area and energy were estimated based on [56] [58]. 5000 TSVs [59] with a pitch of 48 µm × 55µm [60] were used to estimate TSV matrix area, with energy modeled from [56]. Figure 10a,b illustrates the power and area breakdown inside one NST instance.…”