20.5 A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement

Abstract

Reducing the supply voltage of digital circuits to the sub-or near-threshold regions minimizes dynamic power consumption and achieves better efficiency [1]. This technique is widely used in energy-efficient applications, and is especially beneficial for wirelessly powered devices such as wearable electronics, biomedical implants and smart sensor networks. Such devices have long standby times and battery-less operation is highly desirable. As shown in Fig. 20.5.1, for a typical wireless power transmission system, there is a gap between the rectified V IN (>2V) and the low supply voltage V OUT (<700mV) for powering up energy-efficient digital circuits. To bridge this voltage gap without sacrificing compact size, fully integrated power converters with a low voltage conversion ratio (M=V OUT /V IN ) and high efficiency are needed. However, a low M results in low efficiency for linear regulators and fully integrated buck converters. On the other hand, fully integrated switched-capacitor power converters (SCPCs) are good alternatives that can achieve high efficiency at low M in low power applications [2][3][4][5].Reconfigurable SCPC designs with multiple conversion ratios could provide low output voltages and maintain high efficiency [3,4]. In [3], four power stages are cascaded in recursive sequence and achieve 15 linear ratios, providing a low output voltage down to 0.1V. However, this 2-phase SCPC needs many flying capacitors and power transistors. In [4], four conversion ratios are used to support an output voltage range of 0.45 to 1V from a 1.225V input. In [6], 3phase operation was introduced to realize more conversion ratios using the same number of flying capacitors.In this paper, a fully integrated 2-/3-phase reconfigurable step-down SCPC with an input voltage range of 1.5 to 2.5V and an output voltage range of 0.4 to 0.7V is proposed (Fig. 20.5.1). The power stage consists of only 2 flying capacitors and 8 switches (Fig. 20.5.2). For V IN <2V, the converter operates in 2-phase mode with M=1/3; and for high V IN (2-2.5V), it operates in 3-phase mode with M=1/4. For simplicity, consider the no-load case such that capacitor voltages do not change from phase to phase. The 1/3X mode operates with two phases and the subtraction operation is adopted (see Fig. 20.5.3). In Ф 1 , C 2 is stacked on top of C 1 in parallel with C L , and V IN =V C2 +V C1 with V C1 =V OUT . In Ф 2 , C 2 is discharged by C 1 in series with C L , and V OUT =V C2 -V C1 meaning that V OUT =V IN /3. The 1/4X mode operates with three phases. In Ф 3 , we have V C1 =V OUT ; in Ф 1 , V IN =V C2 +2V OUT ; and in Ф 2 , V C2 =2V OUT meaning that V OUT =V IN /4. With the 1/4X mode, efficiencies of low output voltages are improved, and the 3-phase operation requires no additional flying capacitor.For a bulk-CMOS process, MOS capacitors have the highest capacitance density but also have large parasitics that reduce the overall efficiency. Effective alternatives have been reported, such as using ferroelectric capacitors [2] or high-density MIM capacitors ...

12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback

“…12.1.5 compares the output conductance at 2/3 configuration of the rational converter with the most similar ratio configuration of the binary converters, 11/16, showing that 2/3 configuration has higher output conductance, and thus, better efficiency. When compared to some previous few-ratio converters’ configurations [4, 5] (Fig. 12.1.5, bottom), the rational converter has similar or better conductance and efficiency.…”

“…This structure was improved in [2] by reversing the cascading order to increase output conductance and in [3] by using a positive feedback approach. However, this design still provides less output conductance than previous works offering only a small fixed number of ratios [4,5]. This paper presents an SC DC-DC converter that can be reconfigured to have any arbitrary rational conversion ratio: p/q, 0<p<q≤2 N+1 .…”

Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip

“…In fully integrated switching-capacitor converters, the flying capacitors could be implemented by the baseline MOS capacitors [29], deep trench capacitors [30], Metal-Oxide-Metal (MOM) capacitors [20] and Metal-Isolator-Metal (MIM) capacitors [8].…”

P‐58: Efficiency Enhancement by Non‐Overlapping Time Design and Adaptive Ratio Control for Charge Pump of Display Drivers

“…To widen the range of input voltage and output voltage and then improve the total efficiency, more voltage conversion ratios (VCRs) are required while high integration needs be kept [4][5][6][7]. Thus, multi-phase charge pumps are superior since they have achieved efficient utilization of each off-chip capacitor [8][9][10][11]. However, today's multi-phase schemes seldom address the non-overlapping (NON) time of each clock phase, which introduces more unreliability and results in poor product yield.…”

“…However, today's multi-phase schemes seldom address the non-overlapping (NON) time of each clock phase, which introduces more unreliability and results in poor product yield. Only one work dealt with the NON time with break-before-make mechanism [9]. But it is still not suitable for charge pump with high VCR requirement since it would result in high power loss when driving the large transistors.…”