3D chip stacking with C4 technology

Dang, Bing; Wright, S. L.; Andry, Paul; Sprogis, E.; Tsang, C. K.; Interrante, M. J.; Webb, Bucknell C.; Polastre, R.; Horton, R.; Patel, C.S.; Sharma, A.; Zheng, Jian; Sakuma, Katsuyuki; Knickerbocker, John

doi:10.1147/jrd.2008.5388560

Cited by 46 publications

(24 citation statements)

References 18 publications

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“…The vias-last approach enables front-side MLM processing on a full thickness substrate, which eliminates the need for wafer-thinning processes that typically require the use of carrier wafers and associated techniques [4]. However, forming vias in a full thickness wafer typically requires larger TSV dimensions (larger pitch, more real estate) to mitigate aspect ratio (AR) limitations on subsequent deposition and etch processes.…”

Section: Through-si Via Process Modulesmentioning

confidence: 99%

Process integration and testing of TSV Si interposers for 3D integration applications

Lannon

Hilton

Huffman

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules.The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6" wafers. The front-side MLM was comprised of 4 metal routing layers (2 µm Cu with 2 µm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 mΩ per via. TSV dimensions of 100 and 80 µm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 mΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm x 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), waferlevel packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6" wafers. Via dimensions for the viasfirst interposers were 50 µm diameter x 315 µm depth or 80 µm diameter x 315 µm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 µm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

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Section: Through-si Via Process Modulesmentioning

confidence: 99%

Process integration and testing of TSV Si interposers for 3D integration applications

Lannon

Hilton

Huffman

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…This necessitates the development of a process for the temporary attachment of chips, which is particularly valuable in 3D stacking. Figure 6 [21] shows an SEM image of a reworked chip stack on a TCA (temporary chip attach) substrate, after testing. The authors have shown that a rework process can be successfully implemented using a hot shear method to detach the chip from the TCA, and then prepare it for joining to the final substrate [21].…”

Section: D2d (Die To Die) Bondingmentioning

confidence: 99%

“…This has been studied previously using Controlled Collapse Chip Connection (C4) between one thinned die and one full thickness die by Dang et al [21]. With adequate warpage control of the thinned die, and optimization of handling and release methods on wafers, assembly yield of 100% was demonstrated on die containing several thousands of TSV's.…”

Section: Micro Bump Technologymentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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“…Therefore via formation and via filling processes are needed after the bonding process to electrically connect each stacked layer. Metal bonding techniques, such as C4 [14], low-volume solder [1,5,11], and direct Cu-to-Cu [13], are the main candidates for the micro-bumps to form electrical interconnections in 3D integration. Cu-to-Cu bonding is preferred, since Cu has superior heat conductance and low resistance.…”

Section: Introductionmentioning

confidence: 99%

IMC bonding for 3D interconnection

Sakuma

Sueoka

Kohara

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.

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3D chip stacking with C4 technology

Cited by 46 publications

References 18 publications

Process integration and testing of TSV Si interposers for 3D integration applications

Process integration and testing of TSV Si interposers for 3D integration applications

3D integration review

IMC bonding for 3D interconnection

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