45nm CMOS platform technology (CMOS6) with high density embedded memories

Iwai, M.; Oishi, A.; Sanuki, T.; Takegawa, Y.; Komoda, T.; Morimasa, Y.; Ishimaru, K.; Takayanagi, Motowo; Eguchi, Koichi; Matsushita, Daisuke; Muraoka, K.; Sunouchi, K.; Noguchi, T.

doi:10.1109/vlsit.2004.1345364

Cited by 13 publications

(4 citation statements)

References 1 publication

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“…For this purpose, F-PSII is applied to state-of-the-art CMOS fabrication with a NiSi self-aligned silicide (SALICIDE) structure. 18) In order to accentuate its impact, its implantation dosage is set to be È ¼ 1 Â 10 15 cm À2 .…”

Section: Cmos Fabrication With F-psiimentioning

confidence: 99%

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Tsuchiaki

Ohuchi

Nishiyama

2005

Jpn. J. Appl. Phys.

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To date, various connection rerouting methods for connection-oriented mobile networks have been proposed. The previous methods, however, are limited to specific topologies or environments. In this paper, we propose the connection-information-based rerouting widely applicable to various connection-oriented mobile networks. This method requires neither a specific topology nor a complex connection, enables fast rerouting, provides appropriate route optimality, and can be extended easily.

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Section: Cmos Fabrication With F-psiimentioning

confidence: 99%

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Tsuchiaki

Ohuchi

Nishiyama

2005

Jpn. J. Appl. Phys.

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“…The creation of 22nm half-pitch GDR (gridded design rule) structures combines the prior art of (a) 22nm half-pitch SADP intended for NAND Flash array patterning [1,2] with (b) the cutting of array structures for manipulation into nonFlash circuits [3,7,8,9]. To demonstrate the most basic structure, we focused on generating 22nm patterns comprised of both long lines and small islands mixed densely together.…”

Section: Apf Process Sequence For Pitch Halvingmentioning

confidence: 99%

“…SRAM bit cells have used two patterning steps since at least the 45nm technology node [8]. This approach has been considered for over 12 years and has been well documented (see for example [7,9]).…”

Section: Sram Applicationmentioning

confidence: 99%

APF pitch-halving for 22nm logic cells using gridded design rules

et al. 2008

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The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF®-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitchhalving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela Canvas™ implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

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“…Recently, oxynitride gate dielectrics less than 1 nm thick have been reported. 1) Their gate leakage current is significantly high and close to the critical value to ensure the low off-current of MOS field effect transistors (MOSFETs). The development of high-k gate dielectrics is making rapid progress to overcome this problem.…”

Section: Introductionmentioning

confidence: 99%

Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO₂ High-k Gate Dielectrics

Aoyama¹,

Nara²

2005

Jpn. J. Appl. Phys.

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We investigate a MoN x /HfO2 gate stack fabricated using a gate-first process flow. We ideally etch the MoN x /HfO2 gate stack using a Cl2-O2 gas system. The work function variation of MoN x gates is more than 0.7 eV. The work function can extensively cover the energy of the band gap of Si except that near the conduction band. In addition, we show issues on thermal budget from N diffusion in Mo and the reaction of Mo with HfO2. We propose that thin-SiN insertion between MoN x and HfO2, and a decrease in Mo thickness are useful in fabricating process windows. On the basis of the results, we fabricate metal-oxide-semiconductor (MOS) devices and show their excellent characteristics.

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45nm CMOS platform technology (CMOS6) with high density embedded memories

Cited by 13 publications

References 1 publication

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

APF pitch-halving for 22nm logic cells using gridded design rules

Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO₂ High-k Gate Dielectrics

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45nm CMOS platform technology (CMOS6) with high density embedded memories

Cited by 13 publications

References 1 publication

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation

APF pitch-halving for 22nm logic cells using gridded design rules

Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO2 High-k Gate Dielectrics

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Product

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About

Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO₂ High-k Gate Dielectrics