50 nm Al&lt;inf&gt;x&lt;/inf&gt;O&lt;inf&gt;y&lt;/inf&gt; ReRAM array retention characteristics before and after endurance

Yamazawa, Hiroki; Ning, Sheyang; Iwasaki, Takaya; Tanakamaru, Shuhei; Koh, Jung‐Hyuk; Takeuchi, Ken

doi:10.1109/snw.2014.7348598

Cited by 4 publications

(3 citation statements)

References 2 publications

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“…23) However, NVM devices have non-ideal properties such as quantization error of memory device conductance, conductance variation, and wearing out by switching. [24][25][26][27][28][29] Figures 9(a) and 9(b) show the measured conductance variation of an ReRAM memory device 30,31) at Set/Reset 10 4 cycles and 10 6 Set/Reset cycles, respectively. ReRAM can switch between HRS and LRS.…”

Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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This paper proposes tiny and error tolerant Convolutional LSTM (ConvLSTM) for event-based vision sensor (EVS) data processing with Computation-in-Memory (CiM) that utilizes ReRAM. To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error tolerant ConvLSTM CiM, reduction of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and worn out by Set/Reset cycles that induces bit inversion. Thus, bit error rate at each Set/Reset cycles are investigated, and the bit precision of the weight is optimized to accept bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM of that weight is represented in 32-bit precision.

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Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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“…The shift value depends on the level of worn. 29) This simulation platform can also emulate those types of shifts according to measurement data. Note that this simulator platform is currently not capable of manipulating individual weights according to their individual properties.…”

Section: Conductance Shiftmentioning

confidence: 99%

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Higuchi

Matsui

Misawa

et al. 2022

Jpn. J. Appl. Phys.

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This paper proposes a comprehensive computation-in-memory (CiM) simulation platform. The platform has the capability to emulate the degradation of inference accuracy caused by device non-ideality. In this paper, the effect of non-ideality by assuming non-volatile memory devices such as PRAM, ReRAM, MRAM, and FeFET in CiM were investigated. As the device is non-ideality, multi-level cell operation, conductance variation during verify-program, data retention error, sense amplifier offset, read current fluctuation, and device failure are considered. First, the acceptable amount of a single non-ideality was investigated. The results address that the conductance shift has much more of an adverse impact than conductance variation on inference accuracy in CiM. In the second place, interaction among multiple device non-idealities were also comprehensively investigated. The platform reveals paradoxical results that the inference accuracy of the combination of uniform shift and low conductance asymmetric error is higher than that of a single low conductance asymmetric error under specific conditions.

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“…23(b) is measured right after ReRAM array program. On the other hand, data retention error may occur which is caused by cell resistance drift over time [32]. This error may dominant after a long retention time compared to program error.…”

Section: Endurance Extensionmentioning

confidence: 99%

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

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50 nm Al<inf>x</inf>O<inf>y</inf> ReRAM array retention characteristics before and after endurance

Cited by 4 publications

References 2 publications

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

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