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A hybrid storage architecture of ReRAM and TLC (3b/cell) NAND Flash with RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first three approaches, (i) flexible R Ref (FR), (ii) adaptive asymmetric coding (AAC), and (iii) verify trials reduction (VTR), are applied to 50nm ReRAM to improve the bit-error rate (BER) by 69% and performance by 97%. Techniques (iv) balanced bits/cell optimization (BCO) are applied to 2Xnm TLC NAND to reduce the failure rate by 98% and extend the lifetime (write/erase (W/E) cycles) by >22×, respectively.Conventionally, in hybrid ReRAM/MLC (2bits/cell) NAND, high-speed ReRAM is paired in small ratios with high capacity NAND, and data is allocated based on access frequency (i.e., frequently written hot data to ReRAM, cold data to NAND) and data size (i.e., fragmented random data to ReRAM, sequential data to NAND) to enhance the overall system performance, reliability and power [1]. Exchangeable TLC/MLC NAND storage arrays have been proposed [2], as well as application of duplicate data requiring RAID-1 to MLC NAND, for reliability improvement in enterprise servers [3].This work presents hybrid storage of ReRAM and TLC NAND Flash with costeffective RAID-5/6 ( Fig. 19.6.1). RAID-5/6 is widely used in cloud storage and data warehouses due to its lower parity overhead (<10%) compared to RAID-1. Our architecture provides significant improvements in the reliability and performance of ReRAM and TLC NAND. Data to ReRAM is encoded by AAC and then written to ReRAM with VTR. During read, FR determines the optimum read reference resistance, R Ref , to minimize the BER. In the NAND, balanced RAID-5/6 evenly allocates the data among the different page types in order to minimize the worst case RAID failure rate, and BCO decides the mode (TLC/MLC/SLC) to extend the NAND chip's lifetime. Figure 19.6.2 describes FR in ReRAM, based on a 50nm, 64Mb Al x O y prototype, in which verify programming is applied on write units of 1Kb. After each set/reset pulse, verify read checks that the resistances satisfy the threshold levels (R Rst ). The failed cells in the write unit are subjected to increasingly stronger set/reset pulses (voltage-increase for set, and pulse-width increase for reset) until the number of failed cells falls below the acceptable error threshold (E TH ), or the maximum number of verify trials is reached. The average and variance of measured set/reset resistances during cycling are also shown. At each set/reset cycle, the optimum R Ref to minimize the BER is calculated. By adopting a more flexible 2-step R Ref scheme to track with the optimum R Ref , the measured BER is decreased by 65%. Figure 19.6.3 describes AAC in ReRAM. Conventionally, in NAND, data retention causes the dominant error of threshold voltage (V th ) reduction; therefore, simple asymmetric coding is effective to reduce the population of high V TH states [4]....

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This work investigates resistive random access memory (ReRAM) data retention after different set/reset endurance cycles on a 50 nm Mega-bit-class Al x O y ReRAM array. The high resistance state (HRS) before forming and low resistance state (LRS) after forming show the best retention compared with after set/reset programming. When set/reset cycles increase, the LRS retention becomes better, whereas HRS retention gets worse, probably because the filament size becomes larger. Consequently, the retention time of ReRAM is degraded as the device is worn out and the error rate of HRS becomes dominant.

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