700V Lateral DMOS with New Source Fingertip Design

Lee, S.H.; Jeon, C.K.; Moon, Jin-Woo; Choi, Yong-Cheol

doi:10.1109/ispsd.2008.4538918

Cited by 22 publications

(10 citation statements)

References 5 publications

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“…Fig. 4 b illustrates the R on,sp against BV for several power LDMOSs [7–11] compared with the silicon limit given in [12] and the figure of merit (FOM) of these devices is discussed. A trade‐off between the BV and the R on,sp is achieved in the VFP LDMOS.…”

Section: Resultsmentioning

confidence: 99%

Trench SOI LDMOS with vertical field plate

Zhang

Shi

et al. 2014

Electron. lett.

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A novel vertical field plate (VFP) structure with low specific on-resistance (R on,sp) is proposed. The VFP is inserted in the field oxide of the drift region with heavily doped N pillar parallel to the trench oxide layer (TOL), which depletes fully the drift region to decrease R on,sp effectively and enhances the bulk field (ENBULF). The VFP optimises the bulk electric field to increase the breakdown voltage (BV). The BV of VFP is 668 V with an R on,sp of 44.7 mΩ cm 2 , which is much lower than the silicon limit.

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Section: Resultsmentioning

confidence: 99%

Trench SOI LDMOS with vertical field plate

Zhang

Shi

et al. 2014

Electron. lett.

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“…a JTT with P-islands and N-compensations [32] . E max is reduced by the opposite-type doping compensation.…”

Section: Jtt With Reduced Nmentioning

confidence: 99%

Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

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“…To suppress the curvature effect, Komatsu et al proposed a novel LDMOS by increasing the curvature radius in the terminal region, [4] but its manufacturing cost increases with device size increasing. To reduce the electric field in the terminal region, Lee et al optimized the LDMOS by inserting P-type rings around the source fingertip region, [5] but the BV could not be improved remarkably by this method. On the other hand, the electrostatic discharge (ESD) performance of LDMOS is also very important for its practical applications.…”

Section: Introductionmentioning

confidence: 99%

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Xu¹,

He²,

Liang³

et al. 2021

Chinese Phys. B

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A novel terminal-optimized triple RESURF LDMOS (TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolar-CMOS-DMOS (BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage (BV) and electrostatic discharge (ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse (TLP) tests, direct current (DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance (R on,sp) of 6.99 Ω⋅mm2. Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

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700V Lateral DMOS with New Source Fingertip Design

Cited by 22 publications

References 5 publications

Trench SOI LDMOS with vertical field plate

Trench SOI LDMOS with vertical field plate

Review of technologies for high-voltage integrated circuits

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

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