A 0.063 µm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Abstract

We demonstrate the smallest FinFET SRAM cell size of 0.063 μm 2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE 2 ) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

3D Monte Carlo study of scaled SOI FinFETs using 2D Schrödinger quantum corrections

“…In the past, a 3D FE MC simulation toolbox with density gradient quantum corrections [3] demonstrated an excellent agreement with experimental I D -V G of the 25 nm gate length SOI FinFET [8]. The new MC toolbox with Schrödinger equation quantum corrections [6] has no need for any parameter calibration [9].…”

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

“…Beginning with a (100) Si substrate (and devices oriented such that electron transport is along the 110 direction), the FinFETs were formed using the SIT flow to form fins at an aggressive FP of 52 nm (see Table I) with TiN/HfO 2 -based metal-gate/high-κ stack formed using a gate-first flow [3]. Fig.…”

“…1 shows a plan-view scanning electron micrograph (SEM) illustrating tight CPP and FP. Source/drain formation is achieved through an epitaxially grown Si merge process [3], which allows contact pitch (CP) (CP = 104 nm in Table I) to be independent of FP, thus making the process flow for silicide formation and metallization transparent to aggressive FP. The transmission electron micrograph (TEM) cross section in Fig.…”

Energy conserving, self-force free Monte Carlo simulations of semiconductor devices on unstructured meshes

“…Their 3D geometry exhibits non-uniform shapes created by the fabrication process [4,9,10] which leads to new serious challenges for physically based device modelling. In order to precisely describe such fluctuating device geometries, the finite element method (FEM) delivers unrivalled advantages.…”