A 0.6-V 540-nW delta-sigma modulator for biomedical sensors

Yoon, Younghyun; Roh, Hyungdong; Lee, Hyuntae; Roh, Jeongjin

doi:10.1007/s10470-013-0053-7

Cited by 13 publications

(7 citation statements)

References 8 publications

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“…The circuits SDM2 and SDM5 have been mentioned earlier in this paper. The SDM3 circuit is borrowed from a recent paper [20]. Their architectures like CIFF (cascade-of-integrators in feedforward form) and CRFF (cascadeof-resonators in feedforward form) are defined in [4].…”

Section: Test Resultsmentioning

confidence: 99%

A fast SNR estimation method for sigma-delta modulator design

Cheng

Shi

Zhang

2013

2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)

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Section: Test Resultsmentioning

confidence: 99%

A fast SNR estimation method for sigma-delta modulator design

Cheng

Shi

Zhang

2013

2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)

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“…Low power, medium speed, and high resolution Delta-Sigma modulators (DSMs) are indispensable for effective detection of the cardiac signals with frequency band ranging from 0.01 to 300Hz or neural signals with frequency band ranging from sub-1Hz to 100Hz. Recently many DSMs have been reported for implantable biomedical devices in [13,14,15,16,17,18,19,20,21]. Most of the ULV DSMs are implemented by discrete-time (DT) topology.…”

Section: Introductionmentioning

confidence: 99%

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

Chen

Guo

2020

IEICE Electron. Express

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This paper presents an ultra-low-voltage (ULV) high-resolution low-power continuous-time delta-sigma modulator for implantable biomedical devices. The 2 nd -order single-bit modulator adopts feed-forward architecture and a new fully differential ULV amplifier to achieve high signalto-noise plus distortion ratio (SNDR) and power-efficient operation under 0.4-V supply. The amplifier employs a gate-body-input class-AB output topology with a local common-mode-feedback (CMFB) loop to achieve large output swing for less harmonic distortion with low power consumption. A robust clock generator is adopted to ensure modulator's consistent performances across ±10% power supply variation. The modulator is fabricated in a 130-nm CMOS technology with regular V T transistors. The measurement results show that the modulator achieves 75.5-dB SNDR and consumes 6.6-µW under nominal 0.4-V supply within a 500-Hz bandwidth. The achieved SNDR is the best one among the recent reported DSMs operating at 0.4V or below for implantable biomedical applications. The modulator also achieves a 69dB SNDR with 3.7-µW power consumption even operating at 0.32V supply.

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“…A behavioral model is also introduced in ƩΔM in [16], which needs further development for better accuracy. In [18], a ƩΔM is reported using discrete-time (DT) passive loop filter, gives an acceptable performance with low power consumption. The use of large capacitors in loop filters increases the overall size.…”

Section: Introductionmentioning

confidence: 99%

A 159 μW, Fourth Order, Feedforward, Mutli-bit Sigma Delta Modulator for 100 kHz Bandwidth Image Sensors in 65-nm CMOS Process

Prasad¹,

Patri²,

Bashir³

2018

RADIOENGINEERING

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A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor applications is realized in low leakage, high threshold voltage 65 nm CMOS standard process. A top down CAD methodology is used for the design of building blocks, which involves statistical and simulation optimization at different stages of modulator. The multi-bit ƩΔ architecture employs OTA sharing technique with the dual integrating scheme at the first stage and the gain boosted pseudo-differential class-C inverters as OTAs for the rest two stages for low area and power consumption. The operation of proposed ƩΔM is validated through post-layout simulations, considering worst case. The ƩΔM operates at a power supply of 1-V offering a peak signal-to-ratio of 92 dB and a peak signal-to-noise plus distortion ratio of 89 dB for a signal bandwidth of 100 kHz. The overall power and estimated area consumed by the ƩΔM including auxiliary blocks is 159 µW and 101.2 mm 2 , respectively.

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A 0.6-V 540-nW delta-sigma modulator for biomedical sensors

Cited by 13 publications

References 8 publications

A fast SNR estimation method for sigma-delta modulator design

A fast SNR estimation method for sigma-delta modulator design

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

A 159 μW, Fourth Order, Feedforward, Mutli-bit Sigma Delta Modulator for 100 kHz Bandwidth Image Sensors in 65-nm CMOS Process

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