A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

Elmhurst, D.; Bains, R.; Bressie, T.; Bueb, C.; Carrieri, E.; Chauhan, Bharti; Chrisman, N.; Dayley, M.; Luna, Ray; Fan, Kui; Goldman, M.; Govindu, P.; Huq, A.; Khandaker, Murshed; Kreifels, J.A.; Krishnamachari, S.; Lavapie, P.; Loe, K.; Ly, T.; Marvin, F.; Melcher, R. L.; Monasa, S.; Nguyen, Qui; Pathak, B.; Proescholdt, A.; Rahman, Tauhidur; Srinivasan, Balaji; Sundaram, Rammohan; Walimbe, P.; Ward, D.A.; Zeng, Dong; Zhang, H.

doi:10.1109/isscc.2003.1234304

Cited by 15 publications

(2 citation statements)

References 2 publications

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“…N p1 = V th,pg1 / V w1,step1 (6) N p2 = V th,pg2 / V w1,step2 + 1 ( 7 ) where N p1 and N p2 are the number of required program pulse in the first and second steps, respectively. V th,pg1 and V th,pg2 are the change in V th required for programming in the first and second steps, respectively ( V th,pg1 = 4 V and V th,pg2 = 3 V).…”

Section: E Comparison Of Pt For Virtual-ground and Standard Nor Flasmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

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An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtualground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (V th ) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the V th shift caused by the FG-to-FG coupling interference < 25% in the bit-line direction, compared with conventional programming approaches, and the V th shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F 2 /bit (F is the minimum feature size) is successfully implemented into a test chip with good reliability.

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Section: E Comparison Of Pt For Virtual-ground and Standard Nor Flasmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

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“…Another approach is to increase the number of bits per cell, achieved by multilevel memory cell technology (MLC) [2][3] [4][5] [6]. Another approach is to increase the density in vertical dimension which is implemented in this paper with smallest known flash cell-size.…”

Section: Introductionmentioning

confidence: 99%

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

Tran

Sarin

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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An experimental 0.11um 4.5F 2 1.8V multilevel 1Mb vertical floating gate split gate source side injection (SSI) test vehicle for Giga-bit NOR flash memory is shown for the first time. Novel coupled sense line programming for 25mV precise charge placement and novel low cell current ~10ua mode source follower sense amplifier is shown to enable high speed high density G-bit MLC NOR flash memory system.

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NOR Flash memories

Micheloni¹,

Marelli²,

Ravasio³

Error Correction Codes for Non-Volatile Memories

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A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

Cited by 15 publications

References 2 publications

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

NOR Flash memories

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