A 100-MHz 64-tap FIR digital filter in 0.8- mu m BiCMOS gate array

Yoshino, Toshiaki; Jain, Rajeev; Yang, P.T.; Davis, H.E.; Gass, W.; Shah, A.H.

doi:10.1109/4.62185

Cited by 37 publications

(3 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Four filter specifications were selected from the literature: a 64-tap filter [7], a 60-tap filter [8], a 25-tap filter [8], and an 11-tap filter [9]. The design statistics are shown in Table 1, including the number of adders, the number of state registers, the input signal width, the coefficient width, and the output signal width.…”

Section: Resultsmentioning

confidence: 99%

Pseudorandom-pattern test resistance in high-performance DSP datapaths

Goodby

Orailoğlu

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

View full text Add to dashboard Cite

The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testing problem, and the associated fault detection probabilities are derived in terms of signal probability distributions. A method of calculating these distributions is described, and it is shown how these distributions can be used to predict testing problems that arise from the correlation properties of test sequences generated using linear-feedback shift registers. Finally, it is shown empirically that variance matching using associativity transformations can reduce the number of untested faults by a factor of eight over variance mismatched designs.

show abstract

Section: Resultsmentioning

confidence: 99%

Pseudorandom-pattern test resistance in high-performance DSP datapaths

Goodby

Orailoğlu

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

View full text Add to dashboard Cite

show abstract

“…The coefficient bits enter in bit-parallel form and the input data in LSB first bit-skew form. Therefore, w 2 2 delays are required, where w is the length of input data word, Table 2. Comparison of the hardware complexity of the proposed scheme and the two schemes presented in [4,5].…”

Section: Filter Scheme Latency In Clock Cyclesmentioning

confidence: 99%

“…Also, their latency should be low and not proportional to the number of filter taps. The scheme mostly used for the implementation of FIR filters, either in direct or in transposed form, is based on a chain of multiplier-accumulators [1][2][3]. Such a scheme, converted in pipelined form has been presented in the bibliography [4].…”

Section: Introductionmentioning

confidence: 99%

A New Low Latency Parallel FIR Filter Scheme

Kalivas

Vassilakis

Meletis

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.

show abstract