A 15.5mΩcm&gt;sup&lt;2&gt;/sup&lt;-680V Superjunction MOSFET Reduced On-Resistance by Lateral Pitch Narrowing

Saito, Wataru; Omura, Ichiro; Aida, Satoshi; Koduki, S.; Izumisawa, Masaru; Yoshioka, Hironori; Okumura, H.; Yamaguchi, Masakazu; Ogura, T.

doi:10.1109/ispsd.2006.1666129

Cited by 13 publications

(11 citation statements)

References 5 publications

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“…For the SJ devices with V B lower than 100 V, the optimized device was obtained by shrinking the cell pitch with the width of the P-regions only 0.7 to 1 μm [12] . For the SJ devices with V B from 100 to 500 V, the optimized result was realized by the trench epitaxy process with the high aspect ratio [13] . For the SJ devices with V B over 500 V, the optimized device of the multi-epitaxy was obtained by implanting both the N and P regions in a 12 μm cell pitch and the optimized…”

Section: Development Of the Characteristicsmentioning

confidence: 99%

Concept and design of super junction devices

Zhang

Qiao

et al. 2018

J. Semicond.

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The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of Ron∝VB2.5, showing a quasi-linear relationship of Ron∝VB1.03.

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Section: Development Of the Characteristicsmentioning

confidence: 99%

Concept and design of super junction devices

Zhang

Qiao

et al. 2018

J. Semicond.

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“…Nous avons envisagé ce type de structure car les méthodes de fabrication industrielle actuelles se basent sur des implantations fortes énergies [47], [48], ou sur une succession d'épitaxies et d'implantations [34], [41], [49], [50], ou sur une gravure profonde suivie d'une croissance épitaxiale [32], [33], [51]. Ces différentes techniques étant coûteuses, il était intéressant de proposer une solution adaptée à une tenue en tension de 1200 V. La principale différence avec la Superjonction conventionnelle est le profil de dopage de la colonne P ( Figure II.12).…”

Section: Ii241 Présentation De La Structureunclassified

“…Il existe donc une limite entre la dose implantée et la concentration de la couche épitaxiée. Aujourd'hui, les meilleurs transistors SJMOS présentent une taille de cellule élémentaire de 12 μm pour une concentration des colonnes de 3,3.10 15 cm -3 [34].…”

Section: Ii32 Choix Entre Les Deux Structures à Superjonctionunclassified

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

Théolier

2010

E.J.E.E

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“…The super-junction (SJ) VDMOS has attracted a great deal of attention owing to its improvement on the specific onresistance (R on,sp ) and the better trade-off between the R on,sp and breakdown voltage (BV). [1][2][3][4][5][6][7][8] However, the R on,sp is still determined by the doping concentration of the drift region. For high voltage SJ VDMOS, narrowing the width of the pillars is a good choice to improve the N n and reduce the R on,sp , but the fabrication is hard to realize.…”

Section: Introductionmentioning

confidence: 99%

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

Luo

Wei

et al. 2016

Chinese Phys. B

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A new ultra-low specific on-resistance (R on,sp ) vertical double diffusion metal-oxide-semiconductor field-effect transistor (VDMOS) with continuous electron accumulation (CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the R on,sp but also makes the R on,sp almost independent of the n-pillar doping concentration (N n ). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the N n , and further reduces the R on,sp . Especially, the two PN junctions within the trench gate support a high gate-drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the R on,sp by 80% compared with the conventional super-junction VDMOS (CSJ-VDMOS) at the same high breakdown voltage (BV).

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A 15.5mΩcm>sup<2>/sup<-680V Superjunction MOSFET Reduced On-Resistance by Lateral Pitch Narrowing

Cited by 13 publications

References 5 publications

Concept and design of super junction devices

Concept and design of super junction devices

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

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