A 3.6GHz, 16mW &amp;#x03A3;&amp;#x0394; DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS

Linköping Studies in Science and Technology. Dissertations

2015

Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

Section: ∆σ Dac Based Transmittersmentioning

confidence: 99%

“…WiMAX, WiFi (2.4 GHz band), UN-II band (5 GHz band) and UWB (3-10 GHz). Instead, nearly "digital" ∆Σ solutions have been proposed wherein the baseband is up-sampled and digitally processed at a higher frequency [8,26,27,30,31] while the mixing is performed in the analog domain as shown in Figs. 1-10 and 1-11.…”

Section: ∆σ Dac Based Transmittersmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Linköping Studies in Science and Technology. Dissertations

2015

“…The use of high speed digital ∆Σ modulators (DDSMs) has been reported in many ∆Σ DAC based transmitters for WLAN, WiFi, UMTS and WiMAX radio standards [1][2][3][4]. The speed of these DDSMs has so far been limited to 5.4 GHz [2].…”

Section: Introductionmentioning

confidence: 99%

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Alvandpour

2013

2013 Norchip

Abstract-Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ∆Σ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

“…Matlab simulations show that a MASH 1-1 DDSM DAC with seven thermometer-coded current cells (3-bit output) can provide a SNDR of 45-dB at 200 MHz bandwidth and 8-GS/s (OSR = 20) with a current mismatch (σ) of 3.6%. A second order modulator presents only a moderate filtering complexity for suppressing the generated out-of-band quantization noise [2], [3]. For the chosen 1-1 MASH modulator, simulations show that a second order low pass filter can satisfy the spectral mask for the UWB standard in [5].…”

Section: ∆σ Dac Architecturementioning

confidence: 99%

“…O VERSAMPLED ∆Σ DACs have been reported in alldigital [1], "almost" digital [2] and RFDAC [3], [4] transmitters for UMTS, WLAN and WiMAX standards. Their use has been driven by the goal of a software defined radio wherein the bulk of the processing is moved into the digital domain in order to reduce the analog complexity and enable easy reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

IEEE Trans. Circuits Syst. II

Najari

Mesgarzadeh

et al. 2013

Abstract-This paper presents an 8-GS/s, 12-bit input ∆Σ DAC with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR and -57-dBc IMD3, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.