A 3D stackable Carbon Nanotube-based nonvolatile memory (NRAM)

Emerging Memory Devices: Assessment and Benchmarking

“…The proposed mechanism for switching in such an array was the electrostatic repulsion and attraction of the two crossing nanotubes. More recently, a full prototype memory chip IC was demonstrated based on lithographically defined carbon nanotube resistance switching layers [95]. The proposed switching mechanism is fundamentally the same electrostatic resistance switching mechanism reported in reference [94].…”

“…The proposed switching mechanism is fundamentally the same electrostatic resistance switching mechanism reported in reference [94]. However, it was hypothesized in the lithographically defined nanotube layers that the connection and repulsion of many nanotubes in concert is responsible for the observed resistance change [95]. The 4 Mb test chip based on 22 nm carbon nanotube layer memory cells has a typical SET operation requiring a 5 V pulse for 500 ns, with a typical current of 1 μA.…”

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

“…6) Regarding to the potential of reducing NRAM pulse width, prior research shows that NRAM cell intrinsic resistance switching is less than 1 ns for both set and reset. 15,17) 4. Incremental step pulse programming…”

“…Emerging non-volatile memories, such as nano-random access memory (NRAM), resistive random access memory (ReRAM), and phase-change memory (PRAM) have advantages of fast program, large program endurance, and low program voltage compared with conventional non-volatile memory, such as NAND flash. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] Different physical mechanisms can be found on these emerging non-volatile memories. In specific, binary data "0" and "1" is stored in ReRAM by switching the cell resistance between high resistance state (HRS) and low resistance state (LRS).…”

“…The measurement demonstrates characteristics of small cell read current variation over 10 4 write cycles, 50 ns access time, 15 µA cell program current, and stable resistance distributions after 120 °C, 24 h data retention. [15][16][17] However, more measurements are needed to comprehensively investigate the NRAM array program characteristics. This paper is an extension of Ref.…”