A 4GS/s 6b flash ADC in 0.13 μm CMOS

Paulus, Christian; Bluthgen, H.-M.; Löw, Manuel; Sicheneder, E.; Brüls, N.; Courtois, A.; Tiebout, M.; Thewes, R.

doi:10.1109/vlsic.2004.1346637

Cited by 22 publications

(13 citation statements)

References 1 publication

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“…The authors of [6], [10], [17], [18] , [20] and [21] also report effective resolution bandwidths lower than the Nyquist frequency. However, the most common cause is the increased effect of sampling jitter at higher input frequencies.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…However, in Flash ADCs, it has not been used to the same extent. However, in [10] and [6] redundancy was used to increase the yield and provide the desired resolution. The presented ADC utilizes that, with redundant comparators, the accuracy requirement is vastly reduced.…”

Section: Comparator Redundancymentioning

confidence: 99%

“…Redundancy has been used to relax the accuracy requirements of the comparators in [6]. In [7], a combination of redundancy and calibration was used to lower the power dissipation by minimizing the power used by the redundant circuits.…”

Section: Introductionmentioning

confidence: 99%

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A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Sundström

Alvandpour

2009

Analog Integr Circ Sig Process

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Abstract-A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Comparator Redundancymentioning

confidence: 99%

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A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Sundström

Alvandpour

2009

Analog Integr Circ Sig Process

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“…The digital correction in our ADC consists of two parts. First, the (non-monotonic) comparator outputs are converted into monotonic digital M -bit codes (as in [4]). Then follows an (N + 1) × L-bit static look-up table that implements a finer correction: for each of the N +1 quantization bins, the look-up table stores the average of the (measured) upper threshold and the (measured) lower threshold of the bin [7], cf.…”

Section: The Principlementioning

confidence: 99%

“…In [2] and [3], only a fraction of the comparators is actually used: during calibration, those comparators with a threshold close to some ideal threshold are identified and the others are deactivated. In [4], all comparators are used and a digital circuit converts the non-monotonic comparator outputs into monotonic digital codes; in this way, an effective resolution of 6 bits (at very high speed) was obtained from 255 low-precision comparators. The mathematical background of optimal ADC post-correction, as well as an example using experimental ADC data are given in [5].…”

Section: Introductionmentioning

confidence: 99%

On flash A/D-converters with low-precision comparators

Frey

Loeliger

2006 IEEE International Symposium on Circuits and Systems

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Abstract-Flash analog-to-digital converters can be built using small (and fast) low-precision comparators with unpredictable thresholds followed by a digital look-up table to correct the output. The look-up table should store digital codes with higher precision than the nominal resolution of the converter. The effective resolution of such a scheme with N comparators is roughly log 2 (N ) − 1 bits. The concept is demonstrated by a chip that achieves almost 7 bit resolution with 256 low-precision comparators.

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Design of a high‐speed‐sampling stochastic flash analog‐to‐digital converter using device mismatch

Ham

Matsuoka

Wang

et al. 2012

Elect Comm in Japan

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A stochastic flash analog-to-digital converter (SF-ADC) utilizing device mismatch is designed using a 65-nm CMOS process. Since the proposed SF-ADC uses thresholds determined by the input-referred comparator offsets, large input-referred offsets are allowed. The quantization error and nonlinearity of SF-ADC are demonstrated, and the input range is enlarged by using nonlinearity reduction technique. At 1.6 GS/s sampling, the designed ADC achieves 34.7-dB SFDR and 29.0-dB SNDR without any calibration circuits despite the large input-referred offset of 102 mV. At this conversion speed, it consumes 134 mW with a 1.2-V power supply.

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A 4GS/s 6b flash ADC in 0.13 μm CMOS

Cited by 22 publications

References 1 publication

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

On flash A/D-converters with low-precision comparators

Design of a high‐speed‐sampling stochastic flash analog‐to‐digital converter using device mismatch

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