A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission

Abstract

Vitesse Semiconductor, Somerset, NJ Ethernet, SONET and wireless base-station systems transfer data across backplanes of up to 1m in length using NRZ signaling at 1.25 to 3.125Gb/s. Attempts to double the capacity of these systems by transmitting 5Gb/s NRZ data over these FR4 backplanes result in a closed eye due to high frequency attenuation of the traces, crosstalk between connector pins and reflections due to vias acting as open-ended stubs, necessitating adaptive equalization at either the TX or the RX. Achieving 5Gb/s operation over existing backplanes using NRZ signaling as opposed to alternate modulation schemes [1] has been analyzed and will soon be standardized by the optical interconnection forum (OIF) [2]. The NRZ backplane transceiver presented here employs TX pre-emphasis and RX high-frequency boost to partially compensate for high-frequency attenuation and a DFE to cancel ISI without amplifying crosstalk.The RX (Fig. 3.1.1) has a linear front end comprising a continuous-time FFE, an amplifier with a 2-stage VGA, and a 3-tap DFE. This is followed by a bang-bang CDR and a 1:16 DEMUX. Sign-sign-LMS algorithms are used for adapting the coefficients of the FFE, DFE, VGA and DC-offset cancellation circuit. Error signals for the LMS algorithm are generated by slicing the equalizer output at the target ±1 levels. These slicers are in addition to the main slicer set at zero level to detect the polarity of the received data. The LMS algorithm runs at 1/16 times the data rate to save power. The transmission characteristics of the backplane change gradually with temperature and therefore, the adaptation algorithms can run slowly.The FFE is realized by summing the outputs of a fixed-gain DC path and a variable-gain AC path, resulting in a continuous-time IIR filter with a single tunable zero that is adapted to control the amount of high-frequency boost. A continuous-time IIR structure is chosen over the conventional FIR structure to save power and chip area. The first stage of the AC path is a differential pair degenerated by an RC network ( Fig. 3.1.2). Its response is optimized to match the high-frequency roll-off of a backplane trace. The variable coefficient is realized using cross-coupled differential pairs with variable tail currents. The FFE provides a boost of up to 10dB at half the NRZ data rate.The 2-stage VGA following the FFE has variable gain range of 14dB. The variable gain is realized using a cross-coupled differential pair with variable currents (Fig. 3.1.2) in parallel with a differential pair with a fixed tail current. The VGA output is fed to a buffer followed by a pre-amp and a chain of flip-flops. The decision values from the slicers are fed back as differential currents to the buffer output through weighted differential pairs to implement the DFE. A differential DC is also injected into the buffer output for offset cancellation. To detect the error of the equalized signal from the ideal ±1 values, the output of the buffer is fed to 2 comparators whose slicing levels are offset from zero.Th...

A 0.18¿¿m CMOS Receiver with Decision-feedback Equalization for Backplane Applications

“…Another form of equalization is the decision-feedback equalization, or DFE [1][2][3][4][5], which can overcome the drawback of high-frequency noise amplification. DFE uses clean decisions of previously received symbols to remove ISI in the current symbol.…”

“…The exact phase and frequency at the RX is recovered from the data by a digital clock and data recovery loop architecture. In [3], the FFE without the DFE opens the input data eye enough to permit the CDR to achieve lock and thus obtain the clock information for DFE later operation. In [4], the CDR is also parallel to DFE.…”

Recent advances in high-speed serial I/O trends, standards and techniques

“…The feed-forward equalizer (FFE) cancels the precursor ISI while a decision feedback equalizer (DFE) [9] uses a linear combination of past decisions to cancel the post-cursor ISI. In the analog domain, a FFE is realized by summing the outputs of a fixed-gain DC path and a variable-gain AC path, resulting in a continuoustime finite-impulse-response (FIR) filter [10] or an infinite-impulse-response (IIR) filter [11].…”

“…around 12Gb/s). Using an FFE and DFE together addresses these concerns [10,11,[15][16][17]. In [10], a backplane link transceiver architecture, implemented in 0.13µm CMOS technology, incorporates a 4-tap FFE (FIR) that in conjunction with a DFE enables 6.25/12.5Gb/s data transmission.…”

“…In [10], a backplane link transceiver architecture, implemented in 0.13µm CMOS technology, incorporates a 4-tap FFE (FIR) that in conjunction with a DFE enables 6.25/12.5Gb/s data transmission. In [11] a 2-tap preemphasis network in the transmitter, along with a 1-tap FFE (IIR) and 3-tap DFE structure in the receiver is used in a 5Gb/s NRZ transceiver to achieve a BER of less than 10 -15 in the presence of crosstalk.…”