A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

Abstract

This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer (DFE) for applications in wireline communication. A CMOS track-and-regenerate slicer is proposed and employed in the PAM4 receiver. The proposed slicer is designed for the purposes of improving the clock-to-Q delay as well as the output signal swing. A direct DFE in a PAM4 receiver is made possible with the proposed slicer by having rail-to-rail digital feedback signals available with reduced delay, and accordingly relaxing the settling time constraint of the summer. With the 2-tap direct DFE enabled by the proposed slicer, loop-unrolling and inductor-based bandwidth enhancement techniques, which can be area/power intensive, are not necessary at high data rates. The PAM4 receiver fabricated in 28-nm CMOS technology achieves bit-error-rate (BER) better than 1E-12, and energy efficiency of 1.1 pJ/b at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist.

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

“…This makes PAM-4 signaling vulnerable to noise [7]- [9]. Therefore, it is attractive to use decision feedback equalizers (DFEs) in PAM-4 receivers because the equalizers can compensate for inter-symbol interference (ISI) without amplifying the noise [8]. However, the reduced vertical margin of a PAM-4 signal also lengthens the clock-to-Q delay of the slicer.…”

“…In single-ended signaling, which is used in memory interfaces, the clock-to-Q delay can be increased than that in differential signaling. The lengthened clock-to-Q delay makes it difficult to satisfy the timing constraint that requires the PAM-4 DFE to decide data within one UI [8].…”

“…However, an additional phase adaptation is needed to generate the different clocks for each stage, which increases power consumption. In [8], track-and-regenerate slicers are used to increase gain. However, this type of slicer requires a stage to trace the input signal, and this draws an increase in power consumption.…”

“…Another method to improve the clock-to-Q delay in receivers is to increase the peak-to-peak swing of the input of the slicers. The CML amplifier or summer with resistive source degeneration can amplify peak-to-peak swing by adjusting the source degeneration resistors [6], [8]. However, this has a limitation in increasing the gain without increasing power consumption.…”

A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

“…However, the solution increases more noise from DFE circuits because of the small gain of the dynamic latch and is not suitable for PAM‐4 due to the reduced voltage margin. StrongArm comparator (SAC) [3] and modified double‐tail dynamic comparator (DTDC) [4] have advantages of no dc power, high gain, and CMOS‐level outputs, but their large swing and multi‐stage increase the delay. A single‐stage current‐mode‐logic comparator (CMLC) [5] has higher bandwidth and reduced delay, but the regeneration pair induces substantial self‐loading, and there is a trade‐off between bandwidth in the tracking phase and regeneration speed.…”