This brief describes a pseudodigital oscillator design for low-voltage applications. To overcome the start-up problem of the digitally controlled ring oscillator with an ultralow supply voltage, a digitally controlled relaxation oscillator (DCRXO) that utilizes an inverter-based comparator is proposed. The pseudocomparator (PC), which is a variable threshold inverter, followed by an inverter, is introduced and a digital calibration circuit is used to automatically set the threshold of the PC for process-insensitive operation in the initial state. The DCRXO implemented in 65-nm CMOS consumes 17.8 μW from a 0.35-V supply at 26-MHz output and achieves a tuning range of 18.2-29.2 MHz with a sufficient overlap between tuning curves. The phase noise of −104 dBc/Hz at 1 MHz offset is measured at 26-MHz output frequency. When the supply voltage of 0.5 V is used, the DCRXO consumes 59 μW at 100-MHz output with the tuning range of 43.5-152 MHz. The core area of the DCRXO is 0.0362 mm 2 . Index Terms-All-digital phase-locked loop (PLL), clock generation, CMOS, digitally controlled oscillator (DCO), low voltage, oscillator, PLL, relaxation oscillator, voltage-controlled oscillator (VCO).