A charge sharing–based switching scheme for SAR ADCs

Abstract

This paper presents an energy-efficient switching scheme for successive approximation register (SAR) analogue-todigital converter (ADC). The proposed scheme employs charge recycling method to keep the capacitor arrays free of transitional energy between bit generations except reset phase. In comparison with the conventional switching scheme, the proposed one achieves 100% transitional energy saving without considering reset phase. In addition, configuration of a 10-bit SAR ADC shows that the proposed switching scheme reduces the capacitor area by 25% compared with the conventional switching scheme.

An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter

“…Yousefi et al proposed a new switching technique that can achieve 100% energy saving without any sensitivity to the third reference voltage 12 but at the expense of logic complexity. Akbari et al proposed a DAC architecture based on charge sharing switching scheme, which has small reset power consumption 13 . In order to effectively save the conversion energy consumption in the first three steps and make the last comparison without the reference voltage of 1/2 V ref , we propose an energy‐efficient switching scheme.…”

“…Akbari et al proposed a DAC architecture based on charge sharing switching scheme, which has small reset power consumption. 13 In order to effectively save the conversion energy consumption in the first three steps and make the last comparison without the reference voltage of 1/2V ref , we propose an energy-efficient switching scheme. Compared with the traditional switching method, this switching method saves 95.93% of the switching energy and 75% of the DAC area.…”

Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

“…Successive approximation register (SAR) analog‐to‐digital converters (ADCs) generally consume low power in medium resolutions and bandwidths, 1–8 and this property makes them suitable for an extensive variety of applications specifically in energy‐limited applications, 1 multichannel neural recording systems, 2 wearable sensors, 3 and low energy wireless sensor network chips 4 . In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

“…In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

“…In other methods, various techniques such as capacitor splitting, 12 closed‐loop charge recycling, 15 charge‐sharing, 14,16,20 sub‐DAC merged switching, 19 and segmented SAR ADC 23 are used to reduce the DAC switching energy and area. However, except, 11,17,18 any solution is not intended to reduce the number of the required switches in the DAC capacitor array.…”