A Comparative Analysis of Artificial Intelligence for Power Transformer Differential Protection

Afrasiabi, Shahabodin; Behdani, Behzad; Afrasiabi, Mousa; Mohammadi, Mohammad; Liu, Yang; Gheisari, Mehdi

doi:10.1109/eeeic/icpseurope51590.2021.9611033

Cited by 4 publications

(3 citation statements)

References 22 publications

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“…This tool can inject fault in simulated environments by VHDL and Verilog hardware description languages. It should be noted that these tools countered minor problems with VHDL hardware description language, which can be easily encountered by familiarity with VHDL language [22‐24, 30, 36].…”

Section: Fault Injection By Softwarementioning

confidence: 99%

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A novel buffering fault‐tolerance approach for network on chip (NoC)

Jafarzadeh

Jalili

Alzubi

et al. 2022

IET Circuits, Devices & Syst

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Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network-based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance. K E Y W O R D S buffering, error injection, network on chip (NoC), router, virtual channel | INTRODUCTIONNetwork-on-chip (NoC) refers to closed-switch communication in a large VLSI system implemented on a single silicon chip. This concept was introduced to improve the bandwidth of the electrical connections of recent system-on-chips (SoCs). The superiority of NoC interconnects mitigates the challenges of growing to interconnect complexity and power budget requirements, making it significant for scalable architectures. Fault-tolerant routing algorithms are primarily designed to fortify the network against permanent errors. The first valuable designs for NoCs are introduced in Ref. [1][2][3]. In most previous studies, the routing algorithms are designed for situations when one or more areas of the network faceThis is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Fault Injection By Softwarementioning

confidence: 99%

“…Routing algorithms for NoCs are discussed in Ref. [15,17,[22][23][24][25][26][27][28][29], but this study did not consider energy efficiency. However, it did not consider the study of power consumption in NoC.…”

Section: Background and Fault-tolerant Routing Algorithm Designmentioning

confidence: 99%

A novel buffering fault‐tolerance approach for network on chip (NoC)

Jafarzadeh

Jalili

Alzubi

et al. 2022

IET Circuits, Devices & Syst

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“…A single-phase multilevel inverter's performance enhancement can be obtained by the partial shading method, which can be done by cascading the multilevel inverter with the power network [31]. The generalized structure of the cascaded multilevel inverter is further modified with improved converter topology to reduce the total harmonic distortion employing solar photovoltaic applications [32][33][34][35][36][37][38].…”

Section: Introductionmentioning

confidence: 99%

Design of advanced Aalborg inverter for extracting maximum power from renewable energy sources tied with autonomous grid system

Selvaraj¹,

Kumar²,

Tamilarasan³

et al. 2023

IET Power Electronics

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Owing to increased energy demand, renewable energy sources have recently reached greater heights in the power industry. In this regard, integrating renewable energy with the power grid system has become essential in meeting consumer's energy demands. The novelty in this article is the design of an advanced Aalborg inverter with a reduced number of switches which results in enhanced system performance by reducing the switching losses. Integrating renewable energy sources with the power grid network has gained massive importance in supplying electric power to consumers. Integrating the power grid with renewable energy has become possible with the implementation of grid tie inverters. The only drawback in implementing renewable energy sources with the power grid is that the output of the resources varies from time to time in nature. Voltage Source Inverter‐based grid system requires two or three‐stage inverters for interfacing power units to transfer DC energy into the power grid network. To reduce the switching frequency across the system, many new excellent inverters have been designed to ensure the healthy operation of the system operating at a higher frequency. This article has been coined with the investigation of a novel buck and boosts converter‐based inverter operation named Aalborg inverter. The inverter operates at a higher frequency and minimum voltage drop across the inductor, where only one power stage has been implied to enhance the system's reliability and efficiency. This novel Aalborg inverter is applied and investigated for photovoltaic application.

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