A comparative study of advanced MOSFET concepts

Wann, C.; Noda, K.; Tanaka, Tetsu; Yoshida, Makoto; Hu, Chenming

doi:10.1109/16.536820

Cited by 214 publications

(90 citation statements)

References 22 publications

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“…It is unclear whether a single model can tackle the multiplicity of advanced device designs currently under consideration (10). The suitability of the model to different design strategies has to be established.…”

Section: Discussionmentioning

confidence: 99%

An analytical framework for first-order CMOS device design

Alamo¹,

Lynch²,

Antoniadis³

1998

The 1998 International Conference on Characterization and Metrology for ULSI Technology

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We have constructed a simple physics-based analytical framework for MOSFET device simulation. The suite of models is optimized for "well designed" devices that exhibit sufficient electrostatic integrity. This is assessed by means of an analytical model for drain-induced barrier lowering. Using the developed framework, we have simulated 0.1 #m n-channel MOSFETs fabricated at MIT. The agreement obtained between simulations and experiments suggests the viability of this approach in the sub-0.1 #m regime. This analytical framework could form the basis of a compact and efficient first-order CMOS device design environment that could be used to explore key trade-offs and constraints involved in device design several generations ahead. Such a framework could find applications in roadmap planning, sensitivity analysis, and microelectronics education.

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Section: Discussionmentioning

confidence: 99%

An analytical framework for first-order CMOS device design

Alamo¹,

Lynch²,

Antoniadis³

1998

The 1998 International Conference on Characterization and Metrology for ULSI Technology

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“…DG MOSFETs will probably be planar, extremely thin for volume inversion and fabricated with a bonding technology as reported in Scott Thompson et al and G. K. Cellera et al [4,5]. As CMOS scaling approaches the limit the DG-MOSFET has its ability to be scaled to sub 100 nm with better performance, excellent SCEs immunity, higher drain current, volume inversion (VI), higher trans-conductance and steeper sub-threshold slope have been reported by various studies [6][7][8][9][10][11][12][13]. Scaling down improves cut off frequency due to the reduction of supply voltage the analog performance degrades due to SCEs.…”

Section: Introductionmentioning

confidence: 99%

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

Sahu¹,

Mohapatra²,

Pradhan³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

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“…However as we reduce the dimensions, short channel effects (SCEs) cause several problems such as threshold voltage lowering, increased substrate bias effect etc. [1]- [3]. To continue the scaling of Si MOSFETs in the nanometre regime, innovative device structures have been proposed.…”

Section: Introductionmentioning

confidence: 99%