A compute-in-memory chip based on resistive random-access memory

Abstract

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2–5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6–17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

“…After programming, the devices were allowed to de-trap for a minimum of 300ms. A details analysis of the WRITE-to-READ delay on similar devices is shown elsewhere [19]. READ operation was conducted by a voltage ramp with a step size of 100mV at W.L.…”

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications

“…Their real-time data have manifested the need to overcome latency and energy costs induced by the data transfer between the processing unit and memory in von Neumann architecture. Therefore, researchers showed interest in building an in-memory-computing (IMC) based alternative paradigm, − where the computation is done inside the memory, reducing the latency and energy cost. The quintessential example of IMC is vector-matrix multiplication (VMM) with nonvolatile memories (NVMs), which is applied to solve many high-level applications such as neuromorphic computing and to solve computationally tricky problems. − During the execution of VMM for neuromorphic computing, the memory unit must perform computations using single-instruction data sets.…”

Metal–Organic Frameworks–Based Memristors: Materials, Devices, and Applications

“…When the voltage applied between the two electrodes reaches the set voltage and reset voltage, respectively, the resistance value of the switching layer will reversibly switch between a high resistance state (HRS) and a low resistance state (LRS) [14,15], which is several orders of magnitude smaller than HRS. Importantly, lower applied voltages enable memristors to have a characteristic of low power consumption [16][17][18]. Meanwhile, the fabrication process of memristors is compatible with CMOS process technology [19], allowing it to be large cross-bar arrays easily and exhibit a size scalability.…”