2021
DOI: 10.1109/access.2021.3115601
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A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

Abstract: A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the… Show more

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Cited by 9 publications
(6 citation statements)
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“…We will go into detail about the architecture and circuit design of the 16-bit, 500 MS/s SAR-ADC that uses 45 nm technologies [15]. For better performance, the design includes a shared charge double tail dynamic latch (CDTDL) comparator, a Widlar current mirror circuit, and a VTCMOS circuit [16].…”
Section: Introductionmentioning
confidence: 99%
“…We will go into detail about the architecture and circuit design of the 16-bit, 500 MS/s SAR-ADC that uses 45 nm technologies [15]. For better performance, the design includes a shared charge double tail dynamic latch (CDTDL) comparator, a Widlar current mirror circuit, and a VTCMOS circuit [16].…”
Section: Introductionmentioning
confidence: 99%
“…With the advent of a pipelined SAR ADC architecture [6], using a dynamic amplifier (DA) as a residue amplifier has been attracting considerable attentions [7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Since the DA does not draw static current, this approach can lead to a fully dynamic and hence very power-efficient implementation given that the successiveapproximation register (SAR) ADC [21][22][23] in the stage typically does not consume static power.…”
Section: Introductionmentioning
confidence: 99%
“…Moreover, larger driving switches introduce more parasitic capacitance, which reduces the speed of the ADC. The redundancy can alleviate the settling error of a DAC [16][17][18][19][20][21][22][23][24][25][26][27][28]. The nonbinary redundancy [29] needs a complex digital control circuit and an extra an ROM.…”
Section: Introductionmentioning
confidence: 99%