A frame work for model based designing of analog circuits using simulink

Mishra, Bimal Kumar; Save, Sandhya; Mane, Ruturaj

doi:10.1145/1980022.1980290

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…There have also been a few publications about tools for developing synthesizable AMS models. For example, Xilinx System Generator and Simulink HDL Coder have been used to create models for small analog circuits, outside the context of a full chip design [8], [16]. At a much larger scale, F. Nothaft [11] emulated a full cellular modem IC using a tool for converting existing real-number Verilog models of AMS blocks to fixed-point (the tool was not publicly released).…”

Section: Related Workmentioning

confidence: 99%

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst

Rutsch

Ecker

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an open-source framework for emulating mixed-signal chip designs on an FPGA. It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-and floating-point synthesizable Sys-temVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework's generality by discussing three applications: a high-speed link receiver (DragonPHY), a firmware-controlled flyback converter, and an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2-3 orders of magnitude faster than CPU simulations with real number functional models.

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Section: Related Workmentioning

confidence: 99%

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst

Rutsch

Ecker

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Generation and verification of HDL code using MATLAB requires compatible versions of MATLAB (Simulink) and HDL Simulator "Modelsim" to be loaded on the same system [13,14,15]. The basic design steps to create Simulink model for verification of VHDL code in Modelsim HDL Simulator is shown in the flow chart of Fig.…”

Section: Generation and Verification Of Hdl Code Using Matlabmentioning

confidence: 99%

Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

Grover¹,

Soni²

2014

IJIEEB

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-Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.

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