2020
DOI: 10.1109/ted.2020.2975602
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A High Near-Infrared Sensitivity Over 70-dB SNR CMOS Image Sensor With Lateral Overflow Integration Trench Capacitor

Abstract: This article presents a 16-µm pitch CMOS image sensor (CIS) exhibiting a high near-infrared (NIR) sensitivity and a 71.3-dB signal-to-noise ratio (SNR) with a linear response for high-precision absorption imaging. A 1.6-pF lateral overflow integration trench capacitor (LOFITreC) was introduced in each pixel to achieve a very high full well capacity (FWC), and a very low impurity concentration p-type Cz-Si substrate with a low oxygen concentration was employed for improving the NIR sensitivity. The developed CI… Show more

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Cited by 23 publications
(9 citation statements)
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“…For SNR, Murata and Fujihara et al presented a pixel with a high SNR of 70 dB ( Murata et al, 2020 ; Fujihara et al, 2021 ). The pixel size was 16 × 16 μm, and ultra-large capacitances were achieved with in-pixel capacitors.…”
Section: Discussionmentioning
confidence: 99%
“…For SNR, Murata and Fujihara et al presented a pixel with a high SNR of 70 dB ( Murata et al, 2020 ; Fujihara et al, 2021 ). The pixel size was 16 × 16 μm, and ultra-large capacitances were achieved with in-pixel capacitors.…”
Section: Discussionmentioning
confidence: 99%
“…Thus, there is potential to make the circuit configuration per pixel more complex. This strategy can increase the effective pixel capacitance and improve the SNR using a self-resetting circuit [24], [25] or a self-resetting circuit [26]- [28]. In the case of high spatial resolution, techniques for reducing crosstalk, such as a vertical waveguide structure deep trench isolation, are required.…”
Section: B Signal-to-noise Ratiomentioning
confidence: 99%
“…The concentration of DPW was optimized to suppress the leakage and to obtain a high uniformity of the capacitance value over the operating voltage range. Detailed information of optimizations of trench capacitor formation process and DPW conditions as well as transmission electron microscope (TEM) images of the trench capacitors can be seen elsewhere [11], [12]. In addition, distances between adjacent edges of PDs are arranged equally in all the directions to reduce the variation of crosstalk by making the potential between pixels symmetrical.…”
Section: Developed Cis a Circuit Architecture And Operationmentioning
confidence: 99%
“…For instance, to achieve 70-dB SNR, over 10-Me − FWC is needed. There are several technologies to increase FWC, such as using organic photoconductive with high-density capacitors [6], [7], complementary carrier collection [8], and lateral overflow integration capacitor (LOFIC) [9]- [11]. In the LOFIC method, PD, FD, and LOFIC can be optimized independently.…”
mentioning
confidence: 99%