A low power 256 KB SRAM design

Bhaumik, Basabi; Pradhan, Pratap Chandra; Visweswaran, G.S.; Varambally, R.; Hardi, A.

doi:10.1109/icvd.1999.745126

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…In addition, we investigate the design of low power decoder designs for the cache. Various decoder designs have been investigated [6,7] for speed and power in the past. In this paper, we analyze six different decoder structures for their power efficiency.…”

Section: Introductionmentioning

confidence: 99%

A comparative study of power efficient SRAM designs

Hezavei

Narayanan

Irwin

2000

Proceedings of the 10th Great Lakes Symposium on VLSI

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Section: Introductionmentioning

confidence: 99%

A comparative study of power efficient SRAM designs

Hezavei

Narayanan

Irwin

2000

Proceedings of the 10th Great Lakes Symposium on VLSI

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“…As mentioned earlier, power-efficient SRAM is the heartland of our technology savvy mass market, which serves as a viable contender for cache memories [124][125][126]. Its memory capacities have been quadrupling from one generation to another almost every three-yearly [107].…”

Section: Sense Amplifiermentioning

confidence: 99%

CMOS VLSI subsystems for low-voltage low-power applications

Kong¹

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My journey of PhD candidature at NTU has been a worthwhile experience, which is both challenging and fulfilling. In fact, in every important passage of our lives, there are always bound to be some special individuals whose support and contribution are essential in determining our success or failure. In my endeavor of pursuing PhD, the first person to whom, I want to thank is none other than my dissertation advisor, Associate Professor Yeo Kiat Seng. I would like to express my deepest gratitude to him for his willingness and readiness to invest time into giving me adequate and timely guidance despite his very tight schedule. The numerous discussion and brainstorming sessions with him were intellectually inspiring and enlightening. The continuous support and confidence he bestowed upon me was invaluable in steering this dissertation to completion through all its phases. It is also my great pleasure to express my heartfelt appreciation to Associate Professor Chang Chip Hong for sharing his expertise with me and providing insightful comments on my research work. I would like to extend my special thanks to the technical staffs of the Centre for Integrated Circuits and Systems (CICS), Mr. Sia Liang Poo, Mr. Jimmy, and Mr. William for the countless help and assistance they have been offering me throughout my stay in the laboratory. Next, to my peers Gu Jiangmin, Phyu Myint Wai, Chia Leong Yap, Li Qiang, He Yajuan, and Liu Haiqi, thanks for your genuine acquaintance and I will never forget the many wondrous moments we have spent together. The beautiful moments will be forever fresh in mind. Last but not least, I would like to convey my heartfelt appreciation to my parents, siblings and my loved ones for steadfastly standing by me throughout the years, through thick and thin. Words can never express the warmth and thankfulness I feel for each one of them. I want to thank my dear husband, Kam Chew, for his enormous support and endless love, patience and encouragement. The unwavering trust and wholehearted support he has given me all this while will be eternally engraved into my memory. With this, I dedicate this doctorate to them.

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“…; block size AR_1bit = 0.5 ;;;;;;Calculate row and col for equal aspect ratio ar = log(w* AR_1bit)/log (2) ;aspect ratio for 1 wordsize block k = int(log(block)/log (2) ;yheight = address+3 control signals on both sides ; yheight = 1.4*(halfadr+2)+3.9-1.8 yheight = 1.4*(k-halfadr)+4.7…”

Section: Call Top-level Function: Sram_compiler(library Cellview Wordmentioning

confidence: 99%

Development of a low-power SRAM compiler

Jagasivamani

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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i $EVWUDFWConsiderable attention has been paid to the design of low-power, highperformance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM.In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption.Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion.ii With the increasing use of portable consumer electronics, power consumption has become an important performance characteristic for a chip due to both limited battery life in portable systems and also due to expensive packages and heat sinks required by high power levels. Consequently, the design of low-power digital systems is becoming increasingly important. With memories typically accounting for the largest share of power consumption in a system, an emphasis has been placed on the design of low-power memories.More than half of the transistors in today's high performance microprocessors are devoted to cache memories and this ratio is expected to increase in the foreseeable future.Typically, SRAM (Static Random Access Memory) is the choice for embedded memories as SRAM is robust to the noisy environment in such chips. As a result, considerable attention has been paid to the design of low-power, high-performance SRAMs since they are a critical component in both hand-held devices and high-performance processors.A key in improving the performance of the system is to use an optimum sized SRAM. By incorporating an SRAM that is the correct size for the system requirements, the system can avoid using unnecessary memory cells. This leads to improvements in area, speed, and power. Therefore, depending on the application's need, an appropriate SRAM size should be used.In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler will generate an SRAM layout based on a given SRAM size, input by the user. Also, the compiler allows the user to choose between fast vs. low-power SRAM. The SRAM memory array is partitioned into blocks in order to reduce the total power consumption. The Cadence design environment is used for this thesis. Cadence SKILL language is used to implement the compiler and Cadence Virtuoso is used for the layout-editor tool.The organization of the thesis is as follows. In Chapter 2, the background related to the the...

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A low power 256 KB SRAM design

Cited by 5 publications

References 7 publications

A comparative study of power efficient SRAM designs

A comparative study of power efficient SRAM designs

CMOS VLSI subsystems for low-voltage low-power applications

Development of a low-power SRAM compiler

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