A low power consumption inverter-based ΣΔ interface for capacitive accelerometer

IEICE Electron. Express

Guo

2020

This paper presents an ultra-low-voltage (ULV) high-resolution low-power continuous-time delta-sigma modulator for implantable biomedical devices. The 2 nd -order single-bit modulator adopts feed-forward architecture and a new fully differential ULV amplifier to achieve high signalto-noise plus distortion ratio (SNDR) and power-efficient operation under 0.4-V supply. The amplifier employs a gate-body-input class-AB output topology with a local common-mode-feedback (CMFB) loop to achieve large output swing for less harmonic distortion with low power consumption. A robust clock generator is adopted to ensure modulator's consistent performances across ±10% power supply variation. The modulator is fabricated in a 130-nm CMOS technology with regular V T transistors. The measurement results show that the modulator achieves 75.5-dB SNDR and consumes 6.6-µW under nominal 0.4-V supply within a 500-Hz bandwidth. The achieved SNDR is the best one among the recent reported DSMs operating at 0.4V or below for implantable biomedical applications. The modulator also achieves a 69dB SNDR with 3.7-µW power consumption even operating at 0.32V supply.

Section: Introductionmentioning

confidence: 99%

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

IEICE Electron. Express

Guo

2020

“…Moreover, the SC circuits require large GBW of amplifiers, which in turn lead to high power consumption. Recently, inverter-based OTAs are adopted to implement power-efficient DT DSMs in [13,14,15,25,26,27,28]. They achieve high power efficiency, however, at the cost of sacrificing other performance metrics, such as worse power supply rejection ratio, vulnerability to V DD variation and circuit parasitics [29].…”

Section: Introductionmentioning

confidence: 99%

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback

IEICE Electron. Express

Wang

Zhang

et al. 2019

This paper presents a 0.4-V continuous-time delta-sigma modulator for high-quality power-efficient audio applications. A new ultra-low voltage amplifier for high linearity and low power consumption is proposed by exploring class-AB topology with a novel local common-mode-feedback loop. A low V T self-body-biased PMOS switch is employed in feedback digital-to-analog converter to improve the linearity performance against PVT-induced on resistance variation, which avoids clock boosting that may harm long-term reliability. A simple and robust non-overlapping clock generation circuit is proposed for high SNDR performance of modulator at 0.4-V or below. Fabricated in a 130-nm CMOS process, the modulator achieves 90.2 dB signal-to-noise-plus-distortion ratio (SNDR) with 0.2 pJ/step Figure-of-Merit (FoM) over a 20-kHz signal bandwidth, outperforming the reported audio delta-sigma modulators operating at 0.5-V or below. Furthermore, the modulator can operate with a supply down to 0.34-V while achieving an 86.1 dB SNDR at 0.17 pJ/step.

“…The switched-capacitor (SC) amplifier is widely used in various low-power, high-precision analog circuits, such as sample-and-hold circuits [1,2], instrumentation amplifiers for intelligent sensors in strain, pressure and temperature measurement [3], micro-electromechanical systems (MEMS) capacitive accelerometers [4], multi-parameter sensing micro-systems [5], and readout amplifiers for biomedical signal acquisition systems [6][7][8]. Those amplifiers should have a very low DC offset and DC gain error as the output signals detected by the sensors are low-frequency and low-level.…”

Section: Introductionmentioning

confidence: 99%

A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Guo³

et al. 2019

Electronics

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.