A novel test generation approach for parametric faults in linear analog circuits

Zheng, Hong; Balivada, Ashok; Abraham, Jacob A.

doi:10.1109/vtest.1996.510895

Cited by 23 publications

(5 citation statements)

References 15 publications

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“…The analog circuit is mapped to a digital representation using a standard continuous to discrete transformation. This technique is proposed as a more cost effective simulation-based means of analog test generation [97]. This type of R&D activity has to grow to critical mass if the escalating costs of mixedsignal and RF IC testing are to be countered.…”

Section: New Paradigm For Mixed-signal and Rf Testingmentioning

confidence: 99%

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Grochowski

Bhattacharya

Viswanathan

et al. 1997

IEEE Trans. Circuits Syst. II

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Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal IC's. For many years the market growth and technology advancements in digital IC's were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of mixed-signal IC's. The recent advances in wireless communications indicate a trend toward the integration of the RF and baseband mixed signal technologies. In this paper we examine the developments in IC testing form the historic, current status and future view points. In separate sections we address the testing developments for digital, mixed signal and RF IC's. With these reviews as context, we relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.

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Section: New Paradigm For Mixed-signal and Rf Testingmentioning

confidence: 99%

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Grochowski

Bhattacharya

Viswanathan

et al. 1997

IEEE Trans. Circuits Syst. II

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“…Recall that for analog circuits, the test signals should be continuous in the time domain and in their value range. Analog faults depend on the device parameters [8][9][10][11], but the fault models used in these approaches are defective because of the discrete fault values. Thus, these approaches are most suitable for detecting faults that can be explicitly enumerated and are not suitable for parametric faults.…”

Section: Introductionmentioning

confidence: 99%

Test generation algorithm for analog systems based on support vector machine

Long

Wang

2010

SIViP

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In some methods for test generation, an analog device under test (DUT) is treated as a discrete-time digital system by placing it between a digital-to-analog converter and an analog-to-digital converter. Then the test patterns and responses can be performed and analyzed in the digital domain. We propose a novel test generation algorithm based on a support vector machine (SVM). This method uses test patterns derived from the test generation algorithm as input stimuli, and sampled output responses of the analog DUT for classification and fault detection. The SVM is used for classification of the response space. When the responses of normal circuits are similar to those of faulty circuits (i.e., the latter have only small parametric faults), the response space is mixed and traditional algorithms have difficulty in distinguishing the two groups. However, the SVM provides an effective result. This paper also proposes an algorithm to calculate the test sequence for input stimuli using the SVM results. Numerical experiments prove that this algorithm can enhance the precision of test generation.

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“…One of the earliest test generation techniques presented by Tsai [15], formulates test generation as a quadratic programming problem to maximize the difference between the fault free and faulty responses of the CUT. A novel method for test stimulus generation presented in [16] uses a digital test generation tool as the core test generator to obtain an efficient test stimulus for analog circuits. In [17], Balivada, Chen and Abraham use a saturated ramp as the test stimulus for linear analog circuits.…”

Section: Introductionmentioning

confidence: 99%

Enhancing test effectiveness for analog circuits using synthesized measurements

Variyam

Chatterjee

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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The use of alternate tests in addition to specificationbased measurements is achieving more recognition in industry due to the higher coverage that they provide. The fault and yield coverages of these tests depend on how the pass/fail test decision is made. In this paper, we address the critical issue of accurate test threshold determination for these alternate tests. We propose to post-process the given set of sensitive and linearly independent measurements to synthesize a new set of measurements based on which the pass/fail decision is made. A novel methodology for post processing the measurement results called measurement synthesis is presented. Simulation results show that test effectiveness can be greatly enhanced by measurement synthesis. IntroductionTraditionally, analog circuits are tested for parametric variations by verifying the functional specifications of the circuit. In the past, there has been a lot of effort towards reducing the specification testing time by eliminating unnecessary specification tests and ordering them in an optimal way [1-4]. Nevertheless, specification-based testing is still time consuming and expensive. It is reported in [5] that in mixed-signal circuits, 95% of the test cost is expended in testing the analog parts, while the digital counterparts account for only 5% of the overall test cost. In the recent past, researchers have proposed various methods for designing alternate tests for detecting catastrophic and parametric failures in analog circuits. These alternate testing schemes can be broadly classified into DC (static), AC (steady state) and transient (dynamic) testing. Below, we summarize recent work in alternate test design.In [6], the authors propose adding extra tests during wafer probe so that many obviously faulty circuits can be eliminated from the production line at an early stage. Marlett and Abraham [7], and Devarayanadurg and Soma [8] give algorithms for computing DC tests for detecting catastrophic faults. However, parametric faults caused by global process variations like mask misalignment and line width variations, resulting in degradation of circuit performance, are hard to detect using static DC tests. Nagi et. al. in [9], present an algorithm for test frequency selection for AC test using behavioral level fault models and fast fault simulation. In [10], the authors present a test generation algorithm for detecting single and multiple faults based on circuit sensitivity computation. In [11], this is further extended to generate test frequencies for catastrophic faults. However, the catastrophic faults considered are limited to opens and shorts in the passive components. In [12], the authors present an automated tool for sensitivity analysis and test generation called LIMSoft. In this paper they generalize the test generation algorithm presented in [11] to include shorts between any two arbitrary nodes in the circuit under test (CUT). In [13], Abderrahman et. al. solve the test frequency selection problem by formulating it as a minimax optimization problem....

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A novel test generation approach for parametric faults in linear analog circuits

Cited by 23 publications

References 15 publications

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Test generation algorithm for analog systems based on support vector machine

Enhancing test effectiveness for analog circuits using synthesized measurements

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