A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation

Fateh, Schekeb; Schonle, Philipp; Bettini, Luca; Rovere, Giovanni; Benini, Luca; Huang, Qiuting

doi:10.1109/tcsi.2015.2477580

Cited by 51 publications

(16 citation statements)

References 34 publications

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“…10. 1) Sampler: First, the incoming data is sampled with a high-speed sampler which is implemented as a Sense Amplifier based Flip-Flop [30]- [35]. The Sense Amplifier based Flip-Flop has a fast sense amplifier input with a short capture window followed by a slower regenerative latch (Fig.…”

Section: A Bb-pd and Subsamplingmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

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Section: A Bb-pd and Subsamplingmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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“…3) SAR-ADC: In this fully differential SAR-ADC design [25], the sampling/settling time and the bias current of the analog buffers are programmed for each of the successiveapproximation steps. A majority voting mechanism after the SAR-ADC dynamic comparator is employed to reduce thermal noise floor while Cascaded Integrated Comb (CIC) filters further lower it while performing downsampling.…”

Section: A the Biomedical Soc Architecturementioning

confidence: 99%

A sub-10mW real-time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC

Benatti

Rovere

Bosser

et al. 2017

2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)

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Real-time biosignal classification in powerconstrained embedded applications is a key step in designing portable e-health devices requiring hardware integration along with concurrent signal processing. This paper presents an application based on a novel biomedical System-On-Chip (SoC) for signal acquisition and processing combining a homogeneous multi-core cluster with a versatile bio-potential front-end. The presented implementation acquires raw EMG signals from 3 passive gel-electrodes and classifies 3 hand gestures using a Support Vector Machine (SVM) pattern recognition algorithm. Performance matches state-of-the-art high-end systems both in terms of recognition accuracy (> 85%) and of real-time execution (gesture recognition time 300 ms). The power consumption of the employed biomedical SoC is below 10 mW, outperforming implementations on commercial MCUs by a factor of 10, ensuring a battery life of up to 160 hours with a common Li-ion 1600 mAh battery.

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“…Battery systems have advanced especially in the past two decades and have been developed for a wide range of applications, such as electric vehicles, consumer electronics, and medical devices, among others [1][2][3][4][5][6][7][8]. With the increasing demand for cost and size reduction and improved performance, additional advanced functions in a smaller size are increasingly being included in advanced battery systems.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of bi‐directional single‐inductor multi‐input battery system with state‐of‐charge balancing control

Cao

Qahouq

2018

IET power electron.

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This study presents a bi-directional single-inductor multi-input single-output battery system with state-of-charge (SOC) balancing controller. In the discharging operation mode of the battery system, the SOC balancing between multiple batteries is achieved by adaptively modulating the multipliers of the discharging rate of each battery cell, while maintaining the output voltage regulated at the desired value by modulating the average value of duty cycle of the power converter. The SOC balancing is achieved naturally during the operation of the system without extra energy dissipation or charge transfer between the batteries. In the charging operation mode, each battery can be charged independently by using the same bi-directional power stage. The convergence ability of the SOC balancing controller is discussed and results obtained from a proof of concept experimental prototype are presented and discussed in order to evaluate and validate the operation of the controller and system.

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A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation

Cited by 51 publications

References 34 publications

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

A sub-10mW real-time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC

Evaluation of bi‐directional single‐inductor multi‐input battery system with state‐of‐charge balancing control

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