A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS

Mansuri, M.; Jaussi, James; Kennedy, J.; Hsueh, Tzu-Chien; Shekhar, Sudip; Balamurugan, Ganesh; O'Mahony, Frank; Roberts, Clark; Mooney, R.; Casper, Bryan

doi:10.1109/jssc.2013.2279052

Cited by 42 publications

(17 citation statements)

References 15 publications

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“…The PSN analyzer was integrated and measured as part of a high-speed, low-power I/O [15] test chip in 32 nm CMOS. The PSN injector driver is implemented by a NMOS switch array connected between supply and ground with a 5 bit binaryweighted amplitude control.…”

Section: Measurement Resultsmentioning

confidence: 99%

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

Hsueh

O'Mahony

Mansuri

et al. 2015

IEEE J. Solid-State Circuits

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A scalable all-digital power supply noise analyzer with 20 GHz sampling bandwidth and 1 mV resolution is demonstrated in 32 nm CMOS technology for enabling low-cost low-power in-situ power supply noise measurements without dedicated clean supplies and clock sources. This subsampled averaging-based analyzer measures power supply noise in both the equivalent-time and frequency domains with low-resolution VCO-based ADCs. For equivalent-time measurements, the accurate impedance characterization of power delivery networks is simply done by measuring a clock-synchronized current-step response. For frequency-domain measurements, the digital random phase-noise accumulation technique is analyzed and verified to overcome the clock-and-noise correlation issue in autocorrelation measurements. In general large scale integrated circuits and systems, the entire power supply noise analyzer consumes negligible active and leakage powers because of the MHz-range sampling clock frequency and fully digital implementation with only hundreds of logic gates.

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Section: Measurement Resultsmentioning

confidence: 99%

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

Hsueh

O'Mahony

Mansuri

et al. 2015

IEEE J. Solid-State Circuits

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“…The link is targeted to applications whose data rate requirements may span from 4 to 32 Gb/s per lane. Supply voltage scaling, assuming a switching regulator, is employed to ensure that the link power decreases at least linearly with data rate [6]. However, even with supply voltage scaling, a link design solely optimized for performance may exhibit sublinear power scaling with data rate, as circuit blocks with static power consumption degrade power efficiency at lower rates.…”

Section: Link Architecturementioning

confidence: 99%

“…3 shows the bundle and lane clocking architecture. The LC-PLL generates up to an 8 GHz differential clock that is distributed to the two bundles using regulated CMOS buffers similar to the ones used in [6], with a repeater in every bundle. As in [6], CMOS clock distribution is used for its low power consumption, wide frequency range and power efficiency scaling.…”

Section: Link Architecturementioning

confidence: 99%

“…The LC-PLL generates up to an 8 GHz differential clock that is distributed to the two bundles using regulated CMOS buffers similar to the ones used in [6], with a repeater in every bundle. As in [6], CMOS clock distribution is used for its low power consumption, wide frequency range and power efficiency scaling. Optional supply regulation is used to improve the power supply noise rejection of the clocking circuits at the cost of degrading the power efficiency.…”

Section: Link Architecturementioning

confidence: 99%

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A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

Musah

Jaussi

Balamurugan

et al. 2014

IEEE J. Solid-State Circuits

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This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm .Index Terms-Active inductor CTLE, bidirectional link, collaborative CDR, conditional phase detection, decision-feedback equalizer (DFE), phase error decimation, regulated CMOS clocking, source-series terminated (SST) driver.

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“…Exacerbating the described challenges with regard to SI, the rising power consumption of digital systems [6] steadily increases the need for energy-aware design of I/O links, which currently account for about 20% of CPU power dissipationwith a predicted increase to 50% in 2020 [7]. Over the past decade, several approaches have been presented that aim at energy efficiency optimization of electrical links.…”

Section: Introductionmentioning

confidence: 99%

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Müller

Reuschel

Rimolo-Donadío

et al. 2015

IEEE Trans. Electromagn. Compat.

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This paper proposes a novel approach to evaluate design alternatives for high-speed links on printed circuit boards. The approach combines evaluations of signal integrity and link input power. For a comprehensive analysis, different link designs are made comparable through the application of identical constraints, with the link input power as the single figure of merit for a systematic, quantitative comparison of design alternatives. The analysis relies upon a combination of efficient physics-based via and trace models, statistical time-domain simulation, and an analytical input power evaluation, which allows it to handle links consisting of a large number of channels while fully taking into account interchannel crosstalk. The proposed approach is applied to study two fundamental design decisions at the PCB level-singleended versus differential signaling and signal-to-ground via ratios of 1:1 versus 2:1-for a link consisting of 2048 vias and up to 175 striplines with an aggregate data rate of 1 Tb/s. It is found that both design decisions have a considerable impact on the required input power of the link.Index Terms-Energy-aware analysis, high-speed links, printed circuit boards (PCBs), signal integrity (SI), via arrays.

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A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS

Cited by 42 publications

References 15 publications

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

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