A self-aligned CoSi₂interconnection and contact technology for VLSI applications

Investigation of noise sources in platinum silicide Schottky barrier diodes

“…1 The most studied PtSi was formed by conventional furnace annealing ͑CFA͒ of a thin Pt film deposited onto a single-crystal silicon substrate. 2 The rapid thermal annealing ͑RTA͒ technique has been successfully used for fabrication of PtSi/Si Schottky diodes of best performance.…”

Jan Vanhellemont – 35 years of materials research in microelectronics

“…LOCOS-LOCal Oxidation of Silicon) has been systematically investigated leading to a new quantitative model to predict the dislocation type (Burger's vector and habit plane) in function of the stress level, the orientation of the Si substrate and the orientation of the film pattern [1][2][3][4]. The model, originally developed for Si 3 N 4 patterns under a large variety of process conditions, is generally valid and has also been validated for silicide structures [5,6]. Another key achievement resulting from his doctoral research was the understanding of the impact of point defects (interstitials and vacancies) on the nucleation and the growth of both extended defects and precipitates.…”

Suppression of CoSix Induced Leakage Current Using Novel Capping Process for Sub-0.10um node SRAM Cell Technology

“…Co silicide, which can be shrunk down to sub-0.10um width without sacrificing the low resistance characteristics , is indispensable for achieving highspeed operations. However, CoSi 2 has a junction leakage problem because of roughness at CoSi 2 /Si interfaces [2], Co spiking [3], or CoSi 2 agglomeration by the thermal annealing [4]. In order to reduce the junction leakage current, high temperature Co deposition followed by insitu annealing, which could improve roughness at CoSi 2 /Si interfaces [5], and Co/Ti or Co/TiN capping process, which could suppress the agglomeration of the CoSix and the oxygen contamination, had been proposed by other researchers [6].…”