A Sub-μs wake-up time power gating technique with bypass power line for rush current support

Ultra-low power circuit techniques for a new class of sub-mm³ sensor nodes

“…Supply resonance can cause large voltage swings on the supply rails, resulting in the loss of data held in SRAMs and latches because the data-retentive voltage is violated. Supply resonance can be mitigated by gradually stepping the gate voltage of power gating devices [42] or by bypassing resonant current with supply monitors [43].…”

A brief survey on power gating design

“…The problem was firstly considered in [18], which proposed two different structures to control the rush current, a non-uniform sized parallel STs and gate-voltage-controlled staircase-ST. A dual daisy chain structure was proposed in [19] which use a weak chain to trickle the charge, and use the main chain to work under active mode to maintain the performance. Another technique [20] employs an auxiliary power network and extra bypass switches such that the power or ground fluctuation does not affect nearby active circuits that are connected to the other power network. The overhead of these auxiliary power networks and bypass switches can be large.…”

Improvement of power integrity with thin film capacitors embedded in organic interposer

“…Especially, resonant noise on power supply voltage causes fatal impact to power integrity [1]- [3]. Many trails are being made for the countermeasure such as locating on-chip (within LSI) MOS capacitor using high-cost chip area.…”