A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer

Abstract

The aspirations for power efficient ADCs have led to many improvements in this area. In delta-sigma modulators, techniques such as VCO-based quantizer [1,2] and time-domain quantization [3] have been proposed to enhance the overall performance. The former provides additional noise shaping and the latter eliminates the need for the flash ADC. However, in addition to process and temperature variations, the inherent nonlinear behavior of the VCO requires careful attention. The time-domain quantization technique is an efficient way to utilize the quantizer but it does not improve the noise-shaping property. In this paper, we describe modified dual-slope and single-slope ADCs using bidirectional discharging. With a small modification in the discharging phase of these types of ADCs, a first-order quantization noise shaping is attained. These structures may be used as standalone ADCs or as the quantizer in a delta-sigma loop. Moreover, because the modified discharging extracts the quantization error in the analog domain, possibilities exist for further performance improvements [4].The basic operations of the traditional unidirectional dual-slope ADC and the proposed noise-shaped one are shown in Fig. 27.3.1. The input signal is sampled via a resistor in Φ 2 and is discharged in Φ 1 . During the discharging period, a high-speed clock is fed to a digital counter and is incremented. A continuoustime comparator is used to detect the zero crossing of the output and terminates the discharging period. The number of clock pulses fed to the digital counter during the discharging represents the quantized input signal. In the traditional discharging, the termination of the discharge pulse is right at the zero-crossing instance. The proposed discharging technique will continue the discharging until the next edge of the counting clock after the zero crossing. In this fashion, the value stored on the integrator is half-LSB minus the quantization error of the current sample. The next sample of the signal is added to this shifted quantization error before the next discharging phase. Hence, the final digital output code will be (1) showing a first-order noise shaping of the quantization error. The half-LSB offset is a fixed value and can be removed either in the digital or the analog domain. The input sampling via a resistor can provide first-order anti-aliasing for a standalone ADC. However, if this quantizer is to be used in a delta-sigma modulator, it requires a fixed sampled data during its sampling period so that the loop characteristics are not affected. If the discharging is always done in one direction as illustrated, careful common-mode biasing and input sampling are also needed to make sure the output of the opamp always stays above the comparator reference.To overcome these issues, single-slope sampling with bidirectional discharging is proposed. In this implementation, the input is sampled via a switched-capacitor branch to avoid unnecessary windowing of the input. In the discharging phase, the differential output polarity o...

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