1.4V 13&amp;#x03BC;W 83dB DR CT-&amp;#x03A3;&amp;#x0394; modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition

Cannillo, F.; Prefasi, E.; Hernández, Luis; Pun, Ernesto; Yazicioglu, Firat; Hoof, Chris Van

doi:10.1109/esscirc.2011.6044958

Cited by 22 publications

(21 citation statements)

References 7 publications

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“…Compared to the implementations in 0.35-µm CMOS reported in [10], [20] and [21] this work achieves a superior FoM. The achieved FoM is very competitive in comparison to that of the ∆ Σ ADCs in [22], [23] and [24] which have signal bandwidth similar to this work. Featuring an ENOB > 12 bits and power consumption of 6.7 µW in a low-cost CMOS process, the proposed ADC offers an attractive choice for energy-constrained applications such as wireless sensor networks and biomedical implants.…”

Section: Measurement Resultsmentioning

confidence: 48%

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Chen

Harikumar

Alvandpour

2015

Analog Integr Circ Sig Process

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This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .

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Section: Measurement Resultsmentioning

confidence: 48%

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Chen

Harikumar

Alvandpour

2015

Analog Integr Circ Sig Process

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“…Comparison between the result obtained from the proposed method and ideas presented in [5], [6], [7] and [8] has been presented in table 2. …”

Section: Simulation Results Of the Proposed Second Order Delta Sigma mentioning

confidence: 99%

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

Dashtbayazi¹,

Sabaghi

Rezaei³

et al. 2014

JEEE

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Abstract:In this paper, a new structure of delta sigma modulator has been proposed in which a second order filter in one stage technique has been taken into the account and a second order noise shaping method and a third order one have been designed by the proposed idea. In the proposed structure an OPAMP has been saved and since in a conventional delta sigma modulator OPAMPs consumes most of the power and takes very large area, the proposed idea causes less power consumption and also the chip area is minimized.

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“…In the last years multi-bit noise-shaping ADCs using time domain integrating quantizers instead of classical amplitude domain approaches have been successfully implemented in low voltage CMOS technologies, both with continuous time integrators [4] and with switched capacitor circuits [5]. These two approaches meet the requirement of low power and low voltage demanded in biopotential read-out circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Still they have some lacks in terms of power efficiency. The first implementation [4] would need to increase the clock of the system to undesired values to obtain higher resolutions. The second implementation [5] needs high power demanding OpAmps in its discrete time filter to do third order noise shaping.…”

Section: Introductionmentioning

confidence: 99%

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A 1.2V low-power high-resolution noise-shaping ADC using multistage time encoding converters for biomedical applications

Sanjurjo

Prefasi

Hernández

2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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The high-resolution and low power consumption ADCs demand in read-out circuits for biopotential systems has been increased in the last few years. This paper presents a new architecture to implement this kind of ADC´s using multistage time encoding converters. Due to the low voltage supply and low power demanded on this type of applications, the proposed ADC is formed by a second-order multibit noise-shaping converter using a time domain integrating quantizer as first stage and a Differential Gated-Ring Oscillator (DGRO) as second stage of the multistage architecture (MASH). The first-order noise shaping behavior of the DGRO allows to obtain a total third order noise shaping performance in the final ADC output. Moreover, using the arrangement proposed in this work, the low power requirements demanded in biopotential read-out circuits can be achieved. This because the multi-bit flash quantizer used in standard noise-shaping ADCs has been replaced by a time domain integrating quantizer that uses a one bit comparator and a PWM DAC. In addition the second stage of the MASH structure is used to quantize the width of a digital pulse with the benefit of first order noise shaping. Hence, the combination of a GRO with an integrating quantizer may produce a hardwareefficient multistage ADC (MASH) due to the digital nature of the GRO. As an example, the transistor level performance of a MASH 2-1 ADC with the proposed architecture has been evaluated. The transistor level simulations show that the ADC can achieve an ENOB = 15bits in a signal bandwidth of 16kHz using a 0.18μm CMOS technology at 1.2V.

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1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition

Cited by 22 publications

References 7 publications

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

A 1.2V low-power high-resolution noise-shaping ADC using multistage time encoding converters for biomedical applications

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