Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

Stojanović, Vladimir; Ho, A.; Garlepp, B.W.; Chen, F.; Wei, J.; Alon, Elad; Werner, C.; Zerbe, J.; Horowitz, Mark

doi:10.1109/vlsic.2004.1346611

Cited by 52 publications

(18 citation statements)

References 8 publications

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“…In [14] we proposed to use decision feedback equalization (DFE), and will show here that this can be implemented at very low power penalty. DFE is well known in other communication areas, for example in inter-chip communication [18]. Fig.…”

Section: Equalizationmentioning

confidence: 99%

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Mensink¹,

Schinkel²,

Klumperink

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.

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Section: Equalizationmentioning

confidence: 99%

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Mensink¹,

Schinkel²,

Klumperink

et al. 2010

IEEE J. Solid-State Circuits

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“…This operation is commonly done by using an analog summer or by introducing an offset to the slicer [1]. Most summer circuits shown to date are based on a current mode scheme [2,3]; current levels are however high to meet the DFE response time requirements.…”

Section: B Addermentioning

confidence: 99%

A Low-Power Receiver with Switched-Capacitor Summation DFE

Emami

Varzaghani²,

Bulzacchelli³

et al. 2006

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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A low power receiver with a one tap DFE was fabricated in 90nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rateclocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply.

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“…The proposed supply noise measurement circuits were implemented on a 0.13pm CMOS process along with 4 highspeed link cells and a central ASIC that controls and adapts the links [8,9]. The measurement circuits have the capability to measure both the digital logic supply (Vdd) and the supply dedicated to the analog blocks such as the PLL and phase interpolators (vdd,,).…”

Section: Po04 Symposium On Vlsl Circuits Digest Of Technical Papers Mmentioning

confidence: 99%

Circuits and techniques for high-resolution measurement of on-chip power supply noise

Alon

Stojanović

Horowitz

2005

IEEE J. Solid-State Circuits

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132

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A technique for characterizing the cyclically time varying statistical properties and spectrum of power supply noise using only two on-chip samplers is presented. The samplers utilize a voltage-controlled oscillator to perform highresolution analog-to-digital conversion with minimal hardware. The measurement system is implemented in a 0.13pm process as part of a high-speed link transceiver.Measurement results showing the cyclostationary behavior of power supply noise are presented.

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Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

Cited by 52 publications

References 8 publications

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

A Low-Power Receiver with Switched-Capacitor Summation DFE

Circuits and techniques for high-resolution measurement of on-chip power supply noise

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