Aelite: A flit-synchronous Network on Chip with composable and predictable services

Hansson, Andreas; Subburaman, Mahesh Balaji; Goossens, Kees

doi:10.1109/date.2009.5090666

Cited by 73 publications

(76 citation statements)

References 19 publications

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“…In this work we use the logically synchronous AEthereal [26] network with mesochronous links [34]. Figure 1 shows a part of an example instance showing the architectural building blocks, e.g.…”

Section: Physical Scalabilitymentioning

confidence: 99%

“…This step is based on a user specification of the router topology, the link pipeline stages and the number of NIs per router. As detailed in [34], the network uses three-word flits, wormhole switching and source routing. A few basic topology types, e.g.…”

Section: Dimensioningmentioning

confidence: 99%

“…In this work we use a small and fast router design [34], with no restrictions on the network topology. The architectural scalability stems from the ability to arbitrarily add more links, routers, NIs, shells and buses without negatively affecting the services of the existing components [29].…”

Section: Architectural Scalabilitymentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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Section: Physical Scalabilitymentioning

confidence: 99%

Section: Dimensioningmentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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“…In order to give guarantees on bandwidth and/or latency some form of endto-end connections are needed. Solutions to this include nonblocking routers with rate control (e.g., Mango [6]), and circuit switching (e.g., SoCBUS [7]), possibly with time division multiplexing (TDM), (e.g., AEthereal [8], [4]). …”

Section: Related Workmentioning

confidence: 99%

“…The entire design, including the processor cores, the NOC, the memory architecture, and the compiler is being designed with the aim of minimizing the worst-case rather than average-case execution time. This focus on time-predictability, in combination with an aim of keeping the hardware cost low, has caused us to adopt ideas from the time-division-multiplexing (TDM) based NOC designs (e.g., aelite [4]). The TDM scheme supports time predictability in a straightforward way, and the routers and links are extremely simple and efficient.…”

Section: Introductionmentioning

confidence: 99%

An Area-efficient Network Interface for a TDM-based Network-on-Chip

Sparsø¹,

Kasapaki²,

Schoeberl³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IPcores to a packet switched Network-on-Chip (NOC). The functionality of a NI is to bridge between the read/write transaction interfaces used by the cores and the packet-streaming interface used by the routers and links in the NOC. The paper addresses the design of a NI for a NOC that uses time division multiplexing (TDM).By keeping the essence of TDM in mind, we have developed a new area-efficient NI micro-architecture. The new design completely eliminates the need for FIFO buffers and credit based flow control -resources which are reported to account for 50-85 % of the area in existing NI designs. The paper discusses the design considerations, presents the new NI micro-architecture, and reports area figures for a range of implementations.

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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Sethi

Hussin

Hamid

2018

IEEJ Transactions Elec Engng

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Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

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Aelite: A flit-synchronous Network on Chip with composable and predictable services

Cited by 73 publications

References 19 publications

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

An Area-efficient Network Interface for a TDM-based Network-on-Chip

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

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