An Accurate Analysis of Phase Noise in CMOS Ring Oscillators

Pepe, Federico; Andreani, Pietro

doi:10.1109/tcsii.2018.2884569

Cited by 20 publications

(15 citation statements)

References 5 publications

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“…Phase noise is described as the random fluctuation of the phase of an oscillator. Phase noise in ring oscillators has been the subject of many publications, including [30], [36], [37]. The root cause for phase noise is the thermal and flicker noise in the resistors and transistors used in the VCO.…”

Section: A Noisementioning

confidence: 99%

“…Flicker noise is also a major concern in low-bandwidth instrumentation applications. Detailed analysis of the noise in ring oscillators [30], [36], [37] has shown that flicker noise decreases proportionally to the number of oscillator taps. Loosely speaking, it is as if flicker noise is produced by a very large transistor, adding all areas of the inverters in the ring.…”

Section: A Noisementioning

confidence: 99%

“…A good practice is to think of the VCO as if it were an amplifier for the input signal. If one wants good noise in the ring oscillator: use large transistors [37].…”

Section: Design Processmentioning

confidence: 99%

See 2 more Smart Citations

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

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I. MOTIVATION FOR TIME ENCODINGThe scaling of CMOS technology deep into the nanometer range has created challenges for the design of high-performance analog integrated circuits. The shrinking supply voltage and the presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling. Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues. Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance. This article reviews the basic principles of time encoding, in particular applied to analog-to-digital converters (ADCs) based on Voltage-Controlled Oscillators (VCOs), one of the most successful time-encoding techniques to date. Although VCO-based ADCs have been around for a long time [4], [5] they really received a significant boost in interest after Straayer and Perrotts highly cited 2008 paper [6]. Since then, many other advancements from different research groups worldwide have been published, in application domains such as sensor readout [7]-[10], telecom [11]-[13], wideband wireless [14]-[18], Internet of Things [19], automotive [20], [21], biomedical [22]-[24], to name a few. Note that the integrating properties of VCOs have also been used to implement continuous-time filters, time to digital converters and other analog signal processing blocks [25]-[27].This overview article is divided in two parts. This first part will introduce the basic principles of time encoding with emphasis on VCO-based ADCs, and will compare them to traditional analog circuits. The follow-up article (part 2) will describe and compare different time-encoding circuit architectures for analog-to-digital converters, and will discuss the corresponding design challenges of the building blocks. Together, they will demonstrate how time-encoding circuits can overcome many of the problems encountered when designing high-performance analog circuits that fully take advantage of advanced digital CMOS technologies, rather than suffering from it, hence bridging the analog gap to advanced CMOS. The main idea behind time encoding consists of representing an analog signal with a modulated square wave, where the signal information is encoded in the transitions instead of the instantaneous amplitude. Such a signal is easy to handle with digital circuits and is robust against noise and distortion. Representing the signal is then done through pulse modulations, known since long ago. Pulse Width Modulation (PWM) is one of the best examples, and used extensively in, for instance, power electronics. The typical block diagram of a time-encoding ADC is shown in Fig. 1. The analog input signal is applied to a pulse modulator that encodes the information in the pulse width, frequency or position of a signal (or set of signals) with two levels only. This two-level signal, which is still analog, ...

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Section: A Noisementioning

confidence: 99%

Section: A Noisementioning

confidence: 99%

See 1 more Smart Citation

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

View full text Add to dashboard Cite

show abstract

“…The ISF theory suggests that a symmetric oscillating waveform would suppress any flicker noise from up-converting. As an example, by adding more delay stages to a ring oscillator, while maintaining its oscillating frequency, the intrinsic asymmetry in RC-induced rising and falling edges can be mitigated through sharpening of these edges, thus reducing the flicker, 1/f 3 , PN [30]- [32]. Nevertheless, the theory was silent on how to achieve that symmetric oscillation waveform in LC-tank oscillators.…”

Section: Introductionmentioning

confidence: 99%

Oscillator Flicker Phase Noise: A Tutorial

Siriburanon

Staszewski

2021

IEEE Trans. Circuits Syst. II

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“…The traditional NOC consists of a Ring oscillator, NOR gate, and cascaded delay blocks. There are several methods reported for the generation of delay block, which is further used to design the ring oscillator and NOC [4][5][6][7][8][9][10][11][12][13][14]. For low frequency applications, the delay bock should provide more delay.…”

Section: Introductionmentioning

confidence: 99%

Design of efficient delay block for low frequency application

2020

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In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

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An Accurate Analysis of Phase Noise in CMOS Ring Oscillators

Cited by 20 publications

References 5 publications

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Oscillator Flicker Phase Noise: A Tutorial

Design of efficient delay block for low frequency application

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