An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

Niitsu, Kiichi; Shimazaki, Yasuhisa; Sugimori, Yasufumi; Kohama, Yasuaki; Kasuga, Kazutaka; Nonomura, Itaru; Saen, Makoto; Komatsu, Setsuko; Osada, Kensuke; Irie, Naohiko; Hattori, Toshihiro; Hasegawa, Atsushi; Kuroda, Tadahiro

doi:10.1109/isscc.2009.4977517

Cited by 55 publications

(24 citation statements)

References 4 publications

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“…Bandwidth of 5.184Gbps/ch is obtained by circuit simulation. Energy efficiency of the proposed circuit for 2-die stacking is 6.1pJ/b, which is six times larger than the conventional value but it still has an advantage compared to DDR2 interface [2]. For 3-die stacking, the energy efficiency is 9.5pJ/b.…”

Section: Physical Implementationmentioning

confidence: 87%

“…Reference [2] also reports a practical implementation of an inductive-coupling link and it uses hard-macro layout style, in which almost all metal layers are blocked except signal and power terminals. The size of the hard-macro is 486m x 3940m [2] and area efficiency is 0.2mm 2 /Gbps. As a result, the proposed circuit and the design methodology achieve 330 times better area efficiency than ever reported.…”

Section: Physical Implementationmentioning

confidence: 99%

“…Since battery life is always a concern in a mobile system, a lot of efforts have been made to reduce power consumption of a mobile phone system [1]. In order to improve bandwidth and energy efficiency of inter-chip communication, an inductive-coupling link between a processor chip and a memory chip has been proposed [2,3]. Power consumption in [2] is very small and performance is high enough, however, the occupied area is very large, which is not acceptable from a commercial point of view.…”

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confidence: 99%

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A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Shimazaki

Miura

Kuroda

2012

2012 IEEE COOL Chips XV

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I. INTRODUCTIONRecently, mobile internet devices such as a smart phone or a tablet PC are getting popular. All of them require high speed internet connection and various kinds of applications such as a mobile digital TV, two-dimensional / three-dimensional graphics, a video recording, a high resolution camera and so on [1]. Figure 1 shows a simplified block diagram of a high performance mobile phone system. It consists of four major components such as an RF IC, a baseband processor (BB), an application processor (AP) and a memory chip. A baseband processor is an LSI that processes communication functions such like LTE or W-CDMA. An application processor executes operation system and various applications. In this system, bandwidth between AP and BB, or AP and memory needs to be wide enough to realize many wireless applications. Since battery life is always a concern in a mobile system, a lot of efforts have been made to reduce power consumption of a mobile phone system [1]. In order to improve bandwidth and energy efficiency of inter-chip communication, an inductive-coupling link between a processor chip and a memory chip has been proposed [2,3]. Power consumption in [2] is very small and performance is high enough, however, the occupied area is very large, which is not acceptable from a commercial point of view. For area saving, a burst-mode inductive-coupling link has been proposed [4]. Although the burst-mode link can significantly reduce the area, it consumes more transmission power than [2] because it is based on an asynchronous circuit instead of a synchronous one. For substantial area reduction of an inductor, XY coil technique has been proposed [5]. Orthogonal edges of the coil are drawn by using two different metal layers, which enables EDA tools to utilize an area above/below the coil for automated place-and-route (PnR). Multiple-die stacking using an inductive-coupling link has been proposed for some applications to improve performance and energy efficiency at the same time [3,5]. A purpose of this paper is to propose a through-chip interface that consumes small power with less area especially for a mobile phone system and to discuss design methodology for a practical chip design. Figure 2 shows a part of a proposed mobile phone system and its three-dimensional system integration overview. An application processor (AP), a memory chip and a baseband processor (BB) are tightly connected by inductive-coupling links and stacked in a package. In this proposal, the AP is mounted face-down on a package substrate for rich power delivery. Since power and some signals are connected using wire bonding, the memory chip and the BB are mounted face-up on the AP and the memory chip, respectively. Thickness of each chip is assumed to be 80um, which is a little thicker than [4,7,8], because it can be considered more practical value for mass production. The inductive-coupling link shown on the left in figure 2 is used for AP-memory, AP-BB, BB-memory communication, that is, three-die communication. II. HIGH PERFORMANCE AN...

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Section: Physical Implementationmentioning

confidence: 87%

Section: Physical Implementationmentioning

confidence: 99%

mentioning

confidence: 99%

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A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Shimazaki

Miura

Kuroda

2012

2012 IEEE COOL Chips XV

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“…Since coils for inductor can be built with metal wires, no special process technology is needed other than standard CMOS process. It has been used for memory stacking [5], a dynamically reconfigurable processor [6], and a heterogeneous multi-core system [7]. In all of them, straight-forward 3D stacking is used.…”

Section: Introductionmentioning

confidence: 99%

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface

Nakahara

Ozaki

Matsutani

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYThe increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh. key words: inductive coupling interconnect, interconnection network, network on chip

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“…Both technologies have demonstrated high bandwidth density. Inductive-coupling I/O has less stringent chip-to-chip alignment requirements and the ability to drive multiple layers of silicon, although circuit techniques must be used to compensate for crosstalk [6,7]. Although capacitive coupled interconnects have tighter alignment requirements, the crosstalk issues are relaxed [8,9].…”

Section: Introductionmentioning

confidence: 99%

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Sze

Popovic

Shi

et al. 2010

Microelectronics Reliability

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An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

Cited by 55 publications

References 4 publications

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

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