An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

Lee, Sangyeop; Ikeda, Sho; Ito, Hiroyuki; Tanoi, Satoru; Ishihara, Noboru; Masu, Kazuya

doi:10.1109/rfic.2012.6242261

Cited by 12 publications

(6 citation statements)

References 9 publications

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“…To design the target bandwidth when M was 10 and β was 0.85, I CP and C L were decided as 150 μA and 20 pF, respectively, considering the CP noise and the size of the capacitor. The phase margin of the FTL was approximately 88 • according to (4). One of the two poles at the origin in K 0 ( j ω) was cancelled by the effective zero, generated by H RL1 ( j ω) and H RL2 ( j ω).…”

Section: Analysis Of Phase Noise Delay Mismatches and Phase Offmentioning

confidence: 99%

“…In order to resolve this timing issue, recent architectures must use a complex timingcontrol circuit to synchronize the correction timings of the two independent paths, as shown in Fig. 2 [2]- [4]. To overcome the above problems associated with conventional PLL-based PVT-calibrators, recently, there have been many efforts to develop new PVT-calibration architectures that are capable of real-time frequency-tracking without the concerns regarding the timing issue [8]- [19].…”

Section: Introductionmentioning

confidence: 99%

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A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Choi

Yoo

Lim

2016

IEEE J. Solid-State Circuits

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A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltagetemperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was 0.06 mm 2 and total power consumption was 9.5 mW.

show abstract

Section: Analysis Of Phase Noise Delay Mismatches and Phase Offmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Choi

Yoo

Lim

2016

IEEE J. Solid-State Circuits

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“…In the case of designing conventional injectionlocked frequency multipliers (ILFMs), however, there is limitation that output frequencies (f out ) are only integral-multiplied by the reference frequency (f ref As a solution, injection-locked fractional frequency multipliers have been already presented [1,2,3]. However, the proposed circuit in [1] just shows fractional frequency multiplication phenomena due to injection locking without explaining the mechanism.…”

Section: Introductionmentioning

confidence: 99%

“…However, the proposed circuit in [1] just shows fractional frequency multiplication phenomena due to injection locking without explaining the mechanism. Circuits proposed in [2,3] show automatic pulse-selection techniques with respect to the output frequencies, but they need complicated circuit topologies that only allow low-reference frequencies (f ref ). Compared with them, this paper proposes a simple pulse-selection technique to achieve a fractional frequency multiplication, which allows highspeed references to be input.…”

Section: Introductionmentioning

confidence: 99%

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique

Lee

Ito

Tanoi

et al. 2012

IEICE Electron. Express

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An injection-locked fractional frequency multiplier (IL-FFM) based on a ring VCO is proposed. The ILFFM can output signals whose output-frequency step equal quarter of an input reference frequency (1/4 × f ref ), with low-phase-noise characteristics due to injection locking. To realize this fractional frequency multiplication, an injection pulse selection circuit is demonstrated, which can select the appropriate injection pulse trains as to the VCO output phases.

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“…First, the output frequency can only be changed by integer multiples of the reference frequency. The few attempts to extend MDLLs and IL-PLLs to fractionalsynthesis have achieved just coarse frequency resolution [32], [33], preventing their use in practical RF systems. The second problem is the large deterministic jitter, or equivalently the large reference spur, which is mainly caused by the phase offset of the phase detector.…”

mentioning

confidence: 99%

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

Levantino

Marucci

Marzin

et al. 2015

IEEE J. Solid-State Circuits

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Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm^2, and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of -232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of -243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from -32 to -55 dBc

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An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

Cited by 12 publications

References 9 publications

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

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